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| 20001101 x e m i c s data book xx - xe88lc01 / 03 / 05 ultra low-power mixed-signal microcontroller 300 ua at 1 mips 16 + 6 bits adc
xx-xe88lc01/03/05, data book page 2 20001101 preliminary in f ormation copyright xemics printed in switzerland date of release 03-00 03-00-0035 - data book xx-xe88lc01-03-05 xx-xe88lc01/03/05, data book 20001101 page 3 preliminary information table of contents 3 list of figures 9 list of tables 11 1 introduction 15 1.1 conventions used in this document 15 2 xe8000 mcu family 17 2.1 features 17 2.2 family 17 3 power supply 19 3.1 in circuit power supply principle 19 3.2 voltage regulator 20 3.3 voltage multiplier 21 3.4 current requirement 22 4 central processing unit 23 4.1 introduction 23 4.1.1 pipeline 23 4.1.2 gated clocks 25 4.1.3 low frequency modes 25 4.1.4 stand-by mode 26 4.1.5 coolrisc? core features 26 4.2 programmer's model 26 4.2.1 coolrisc? 816 architecture 26 4.2.2 instruction set 26 4.2.3 register bank 31 4.2.4 program memory addressing modes 32 4.2.5 data memory addressing modes 32 4.2.6 flags z, c & v 36 4.2.7 alu output register: a 36 4.2.8 program counter 36 4.2.9 branch conditions 36 4.2.10 call, branch and link 37 4.2.11 events and interrupts 37 4.2.12 pipeline exception 39 4.2.13 halt mode 39 4.2.14 hardware reset 39 4.2.15 low frequency modes 39 5 memory 41 5.1 memory organisation 41 5.2 program memory 41 5.3 data memory 41 5.4 peripherals mapping 42 5.5 address pack 42 5.6 mtp flash memory programmation 42 table of contents xx-xe88lc01/03/05, data book page 4 20001101 preliminary in f ormation 5.6.1 introduction 42 5.6.2 mtp registers 43 6 system operating modes 45 6.1 operating modes 45 6.1.1 start-up and reset states 45 6.1.2 active mode 45 6.1.3 standby mode 45 6.1.4 sleep mode 46 6.2 resets 47 6.2.1 initial reset from the power-on-circuit 49 6.2.2 external reset from the reset pin 49 6.2.3 porta programmed reset combination. 49 6.2.4 watch-dog timer reset 49 6.2.5 buserror reset 49 6.2.6 reset registers 49 6.2.7 oscillators and prescaler control 50 6.2.8 other features 50 6.3 interrupt 50 6.3.1 features 50 6.3.2 overview 51 6.3.3 porta interrupts 51 6.3.4 counters a, b, c and d interrupts 51 6.3.5 prescaler interrupts 51 6.3.6 voltage level detector interrupt 52 6.3.7 acquisition chain interrupt 52 6.3.8 interrupt priorities 52 6.4 events 54 6.4.1 features 54 6.4.2 overview 55 6.4.3 porta events 55 6.4.4 counters a, b, c and d events 55 6.4.5 prescaler events 55 6.4.6 event priorities 55 6.5 miscellaneous 57 6.5.1 port configuration reset 57 6.5.2 prescaler interrupt synchronization 57 6.6 digital debouncer 58 6.6.1 description 58 6.7 system peripheral addresses 58 7 oscillators 59 7.1 rc oscillator 59 7.1.1 rc oscillator principle 59 7.1.2 rc divider cold start 60 7.2 xtal oscillator 61 7.2.1 general description 61 7.2.2 typical external component 61 7.2.3 xtal divider cold start 61 7.2.4 description 61 xx-xe88lc01/03/05, data book 20001101 page 5 preliminary information 7.3 external clock 62 7.4 oscillators control 62 7.4.1 cpu clock 62 7.4.2 oscillator register 63 7.5 prescaler 63 7.5.1 features 63 7.5.2 description 64 7.5.3 registers 65 8 parallel io ports 67 8.1 port a 67 8.1.1 features 67 8.1.2 overview 67 8.1.3 port a configuration 67 8.1.4 porta registers 69 8.2 port b 70 8.2.1 features 70 8.2.2 overview 70 8.2.3 port b digital capabilities 70 8.2.4 port b analog capability 72 8.3 port c 73 8.3.1 features 73 8.3.2 overview 73 8.3.3 port d 75 9 universal asynchronous receiver/transmitter (uart) 77 9.1 features 77 9.2 overview 77 9.3 uart prescaler 77 9.4 function description 77 9.5 interrupt or polling 78 9.6 software hints 78 10 universal synchronous receiver/transmitter (usrt) 83 10.1 overview 83 10.1.1 enabling the serial interface 83 10.1.2 reading the serial interface 83 10.2 registers 83 11 counters/timers 85 11.1 introduction 85 11.2 watchdog 85 11.3 counters 85 11.3.1 overview 85 11.3.2 features 86 11.3.3 block schematics 86 11.3.4 counter registers 86 11.3.5 clock selection 87 11.3.6 16 bit counters 88 xx-xe88lc01/03/05, data book page 6 20001101 preliminary in f ormation 11.3.7 up/down counting 89 11.3.8 capture functions 90 11.3.9 pwm functions 92 11.3.10 counter registers 94 12 voltage level detector 97 12.1 features 97 12.2 overview 97 12.3 vld operation 97 12.4 registers 98 13 power-on reset 99 14 acquisition chain 101 14.1 introduction 101 14.2 block diagram 101 14.3 input signal multiplexing 101 14.4 input reference multiplexing 102 14.5 amplifier chain 102 14.5.1 pga 1 103 14.5.2 pga2 103 14.5.3 pga3 104 14.6 adc 104 14.6.1 input-output relation 104 14.6.2 operation mode 104 14.6.3 conversion sequence 105 14.6.4 conversion duration 105 14.6.5 resolution 105 14.6.6 adc performances 105 14.7 control part 106 14.7.1 starting a convertion 106 14.7.2 clocks generation 106 14.7.3 default operation mode (not yet implemented) 106 14.7.4 registers 106 14.8 acquisition of a sample 108 15 analog outputs 109 15.1 signal dac 109 15.1.1 application 109 15.1.2 typical external components 109 15.1.3 block diagram 109 15.1.4 the generic dac 110 15.1.5 the amplifier 110 15.1.6 signal dac registers 111 15.2 bias dac 113 15.2.1 application 113 15.2.2 typical external components 113 15.2.3 block diagram 113 15.2.4 the dac 113 xx-xe88lc01/03/05, data book 20001101 page 7 preliminary information 15.2.5 the amplifier 113 15.2.6 bias dac registers 114 16 pin-out, package and electrical specifications 115 16.1 xe88lc01 pin-out 115 16.2 xe88lc03 pin-out 117 16.2 119 16.3 xe88lc05 pin-out 119 16.4 electrical specifications 121 16.4.1 absolute maximum ratings 121 16.4.2 operating conditions 121 16.4.3 io pins operation 121 17 index 123 18 contact 125 xx-xe88lc01/03/05, data book page 8 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 20001101 page 9 preliminary information figure 3.1: power supply strategy. 19 figure 3.2: selection of the operation mode with respect to the power supply range. 19 figure 3.3: b) power supply connection for wide voltage operation. 20 figure 3.3: a) power supply connection for low voltage operation. 20 figure 3.4: power supply connection for middle voltage operation. 20 figure 3.5: power supply connection for high voltage operation. 20 figure 4.1: coolrisc 816 core 23 figure 4.2: coolrisc pipeline 24 figure 4.3: pipeline execution of different instructions 25 figure 4.4: direct addressing 33 figure 4.5: indexed addressing 33 figure 4.6: indexed addressing with an immediate offset 34 figure 4.7: indexed addressing with a register offset 34 figure 4.8: indexed addressing with post-modification of the index 35 figure 4.9: indexed addressing with pre-modification of the index 35 figure 5.1: memory organization 41 figure 5.2: mtp registers organisation 43 figure 6.1: system block 45 figure 6.2: sleep mode structure 46 figure 6.3: system operating modes. most peripherals also have several low power modes 47 figure 6.4: power-on reset start 48 figure 6.5: wake from sleep (short reset) 48 figure 6.6: wake from sleep (long reset) 48 figure 6.7: reset in active mode 49 figure 6.8: port configuration reset 57 figure 6.9: prescaler interrupt synchronization 57 figure 7.1: rc programming principle 59 figure 7.2: rc frequencies programming example for low range (typical values) 59 figure 7.3: cpu clock selection 63 figure 7.4: prescaler principle 64 figure 8.1: port a 67 figure 8.2: digital debouncer 68 figure 8.3: port b 70 figure 8.4: port c 74 figure 9.1: example of uart messages 79 figure 11.1: counters/timers block schematics 86 figure 11.2: start synchronization 88 figure 11.3: interrupt generation 88 figure 11.4: counter examples 90 figure 11.5: capture architecture (counter a) 90 figure 11.6: edge detector (1) principle 91 figure 11.7: edge detector (2) principle 92 figure 11.8: pwm output examples 93 figure 12.1: vld timing 97 figure 13.1: reset conditions 99 list of figures xx-xe88lc01/03/05, data book page 10 20001101 preliminary in f ormation figure 14.1: acquisition channel block diagram with zoomingadc? 101 figure 14.2: pga stage principle implementation 103 figure 14.3: conversion sequence. smax is the oversampling rate. 105 figure 14.4: acquisition flow 108 figure 15.1: general block diagram 109 figure 15.2: the dac signal structure 110 figure 15.3: general block diagram of the bias dac 113 16.1 pinout of the xe88lc01 in tqfp44 package 115 16.2 pinout of the XX-XE88LC03 in sop28 package 117 16.2 pinout of the XX-XE88LC03 in tqfp32 package 117 figure 16.1: pinout of the xe88lc05 in tqfp64 package 119 xx-xe88lc01/03/05, data book 20001101 page 11 preliminary information table 1.1: access code convention 15 table 2.1: list of the xe8000 family members functions 18 table 3.1: voltage regulator specifications for rom 21 table 3.2: voltage regulator specifications for mtp 21 table 3.3: regvmultcfg0 21 table 3.4: vmult specifications 21 table 3.5: current requirement of the xe8000 family members 22 table 4.1: coolrisc core main characteristics 26 table 4.2: coolrisc 816 instruction set 28 table 4.3: coolrisc 816 addressing modes 30 table 4.4: coolrisc 816 conditional jump (jcc) conditions 30 table 4.5: coolrisc 816 instruction construction 30 table 4.7: coolrisc 816 registers organization 31 table 4.8: coolrisc 816 interrupts 31 table 4.6: coolrisc 816 internal registers 31 table 4.9: registers roles 32 table 4.10: branch conditions 37 table 4.11: call addresses and priorities 38 table 5.1: program addresses 41 table 5.2: ram addresses 42 table 5.3: peripherals addresses 42 table 5.4: mtp registers 43 table 6.1: system registers 47 table 6.2: enrespconf 49 table 6.3: regsysreset 50 table 6.4: regsysctrl 50 table 6.5: debouncer frequency 50 table 6.6: regsysmisc 50 table 6.7: all interrupts and their priorities 52 table 6.8: interrupt registers 52 table 6.9: regirqhig 53 table 6.10: regirqmid 53 table 6.11: regirqlow 53 table 6.12: regirqenhig 53 table 6.13: regirqenmid 54 table 6.14: regirqenlow 54 table 6.15: regirqpriority 54 table 6.16: regirqirq 54 table 6.17: regirqtest 54 table 6.18: all events and their priorities 56 table 6.19: event registers 56 table 6.20: regevn 56 table 6.21: regevnen 56 table 6.22: regevnpriority 56 table 6.23: regevnevn 57 list of tables xx-xe88lc01/03/05, data book page 12 20001101 preliminary in f ormation table 6.24: regevntest 57 table 6.25: port config reset 57 table 6.26: debouncer frequency 58 table 6.27: system address ranges 58 table 7.1: rc specifications 60 table 7.2: regsysrctrim1 60 table 7.3: regsysrctrim2 60 table 7.4: xtal oscillator specifications. 61 table 7.5: external crystal specifications. 32 khz xtal outside these specifications will must probably delivers correct frequency, but some precision specifications will be released. 61 table 7.6: board design specifications 61 table 7.7: cpu clock selection 62 table 7.8: regsysclock, address h0012 63 table 7.9: frequency examples, typical values for rc setting, range is set to 1 64 table 7.10: automatic input frequency selection, typical values. values in italic are not allowed and may result in unpredictable cpu behaviour. 65 table 7.11: regsyspre0 65 table 8.1: reset selection for each pin 68 table 8.2: clock inputs for counters 68 table 8.3: port a registers 69 table 8.4: register regpain 69 table 8.5: register regpadebounce 69 table 8.6: register regpaedge 69 table 8.7: register regpapullup 69 table 8.8: regpares0 69 table 8.9: regpares1 69 table 8.10: regpatest 69 table 8.11: different portb functions 71 table 8.12: selection for analog lines with regpbdir (pads b0, b2, b4 and b6) or regpbout (pads b1, b3, b5 and b7) 72 table 8.13: port b registers 72 table 8.14: regpbin 72 table 8.15: regpbopen 72 table 8.16: regpbana 73 table 8.17: regpbpullup 73 table 8.18: regpbout 73 table 8.19: regpbdir 73 table 8.20: port c registers 74 table 8.21: regpcout 74 table 8.22: regpcin 74 table 8.23: regpcdir 75 table 9.1: rc frequencies for uart 77 table 9.2: uart internal prescaler 77 table 9.3: baud rate selection 79 table 9.4: word length 79 xx-xe88lc01/03/05, data book 20001101 page 13 preliminary information table 9.5: parity mode 79 table 9.6: parity enable 79 table 9.7: uart registers 80 table 9.8: echo modes 80 table 9.9: reguartcmd 80 table 9.10: reguartctrl 80 table 9.11: reguartrx 80 table 9.12: reguartrxsta 80 table 9.13: reguarttx 80 table 9.14: reguarttxsta 81 table 10.1: serial interface registers 83 table 10.2: regusrtsin 83 table 10.3: regusrtscl 84 table 10.4: regusrtctrl 84 table 10.5: regusrtdata 84 table 10.6: regusrtedgescl 84 table 11.1: regsyswd 85 table 11.2: clock source for counter a 87 table 11.3: clock source for counter b 87 table 11.4: clock source for counter c 87 table 11.5: clock source for counter d 87 table 11.6: cascading counter a & b 88 table 11.7: cascading counter c & d 89 table 11.8: selection for up/down-counting 89 table 11.9: capture source 92 table 11.10: capture function selection 92 table 11.11: pwm1 93 table 11.12: pwm0 93 table 11.13: pwm1 size selection 93 table 11.14: pwm0 size selection 93 table 11.15: counters registers 94 table 11.16: regcnta 94 table 11.17: regcntb 94 table 11.18: regcntc 94 table 11.19: regcntd 94 table 11.20: regcntctrlck 94 table 11.21: regcntconfig1 94 table 11.22: regcntconfig2 94 table 11.23: regcnton 95 table 12.1: voltage level detector operation 97 table 12.2: regvldctrl 98 table 12.3: regvldstat 98 table 13.1: por specifications 99 table 14.1: amux selection 102 table 14.2: pga1 performances 103 xx-xe88lc01/03/05, data book page 14 20001101 preliminary in f ormation table 14.3: pga2 performances 103 table 14.4: pga3 performances 104 table 14.5: adc performances 105 table 14.6: peripheral register memory map 106 table 14.7: peripheral register memory map, bits description 107 table 15.1: dac signal amplifier performances 110 table 15.2: signal dac registers 111 table 15.3: regdascfg0 111 table 15.4: regdascfg1 111 table 15.5: noise shaping setting 111 table 15.6: pwm setting 111 table 15.7: dac status 111 table 15.8: clock setting 112 table 15.9: pwm polarity 112 table 15.10: dac performances 113 table 15.11: amplifier performances 113 table 15.12: bias dac registers 114 table 15.13: regdab1cfg 114 16.1 pin-out of the xx-xe88lc01 in tqfp44 115 16.2 pin-out of the XX-XE88LC03 in so28 and tqfp32 117 table 16.1: pin-out of the xe88lc05 in tqfp64 119 table 16.2: absolute maximum ratings 121 table 16.3: operating conditions 121 table 16.4: io pins performances 121 xx-xe88lc01/03/05, data book 1 introduction 20001101 page 15 preliminary information 1 introduction the xe8000 is a family of microcontrollers (mcu) characterised by their very low power requirement. these mcus are perfectly adapted to manage systems working on batteries or remotely powered. the xe8000 is conceived as an evolutionary family of mcu that can address many applications. as there are always applications that can not be covered by such a product line, xemics also offers full custom asics based on the xe8000, including additional peripherals on request. the intellectual property that the xe8000 relies on, as well as the low power digital libraries, are available from xemics. this document describes the functional components of the xe8000 family and their performance. additional infor- mation relative to specific applications is available as application notes. 1.1 conventions used in this document the negative power supply is named vss. vss is internally connected to the substrate of the chip. unless otherwise stated, all voltages are given with respect to vss. current is positive when flowing into a pin. this pin is said to be sinking current. when the current is going out of the chip, its value is negative and the pin is said sourcing current. all digital words are written from msb to lsb (msb left, lsb right). these words are expressed with all their digits either in binary, decimal or hexadecimal format. when expressed in binary, the word has a b at its beginning, when expressed in decimal, the word has nothing or a d at its beginning, when expressed in hexadecimal, the word has an h at its beginning. unless otherwise stated, all digital signals are active high. regsystem this is a register enablerc this is a bit in a register an unreadable bit will output 0 when read. sometimes the abbreviation for micro- is u instead of m . code bit (register) read-write access r readable w write able c1 readable, cleared by writing 1 c readable, cleared by writing any value table 1.1: access code convention 1 introduction xx-xe88lc01/03/05, data book page 16 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 2 xe8000 mcu family 20001101 page 17 preliminary information 2 xe8000 mcu family 2.1 features the main characteristics of the xe8000 mcu family are ? ultra low power operation ? low voltage operation (1.2 v or 2.4 v to 5.5 v) ? high efficiency cpu ? 1 instruction per clock cycle, for all instructions ? 22 bits wide instructions ? integrated 8x8 -> 16 bits multiplier ? 8 bit data bus ? 64k instruction program addressing space ? 64kb data addressing space ? 8 addressing modes ? mtp (multiple time programmable) memory available ? dual clock (x-tal and/or rc) ? each peripheral can be set on/off individually for minimal power consumption ? uart and synchronous serial interface ? watch dog ? four 8 bit timers with pwm ability ? advanced acquisition path ? fully differential analog signal path for signal and reference ? 4x2 or 7x1 + 1 signal input ? 2x2 reference input ? 0.5 - 1000 programmable gain amplifier ? offset programmed over +- 10 full scale ? 5 - 16 bits resolution adc ? low speed modes with reduced bias current for minimal power consumption ? bias and signal dacs for resistive bridge sensing and analog output ? complete development tools using windows 95 or nt graphical interface ? assembler ? ansi-c compiler ? source level debugger ? cpu simulator ? cpu emulator xe8000hace ? starter kits (in preparation) ? programmer (prostart, includes an eval board) ? hardware emulators (works with xe8000hace, in preparation) 2.2 family the xe8000 family ultra low-power microcontroller is made up of several members, all using the same microproc- essor core and differing by the peripherals available. the xe88lc01 is a low-power sensing microcontroller, based on the xe88lc01, with an advanced acquisition path including diferential programmable gain amplifiers and a high resolution analog to digital converter. its main appli- cations are dataloggers and process control. the xe88lc02 is a low-power sensing microcontroller, based on the xe88lc01, with an additionnal lcd driver. its main applications are metering and dataloggers. the xe88lc03 is a low-power, low-voltage, general purpose microcontroller. its main features are the very efficient coolrisc core, the low voltage function and the real time clock. its main applications are low voltage control and supervision. xe88lc03 will be superseeded by the xe88lc06 later this year. 2 xe8000 mcu family xx-xe88lc01/03/05, data book page 18 20001101 preliminary in f ormation the xe88lc04 is a low-power, low-voltage, general purpose microcontroller, based on the xe88lc03, with an ad- ditionnal lcd driver. its main features are the very efficient coolrisc core, the low voltage function and the real time clock. its main applications are low voltage control and supervision. the xe88lc05 is a low power sensing microcontroller, based on the xe88lc01, with analog outputs. its main ap- plications are piezoresistive sensors and 4 - 20 ma loops systems. other microcontrollers derived from the xe8000 family members can be produced on request, either as new stand- ard products or as customer specific circuits. xe88lc01 xe88lc02 xe88lc03 xe88lc04 xe88lc05 xe88lc06 supply voltage 2.7 - 5.5 v 2.4 - 5.5 v 2.7 - 5.5 v 1.2- 5.5 v for rom 2.4 - 5.5 v for mtp 2.7 - 5.5 v 1.2- 5.5 v for rom 2.4 - 5.5 v for mtp max speed 2 mips 4 mips 2 mips 4 mips at 2.4 v 2 mips 4 mips at 2.4 v operating temperature -40 - 85 c -40 - 85 c -40 - 125 c -40 - 85 c -40 - 85 c -40 - 85 c -40 - 85 c -40 - 125 c cpu coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier coolrisc 816, 22 bits instructions 8 bits data hw multiplier program memory 8k instructions = 22 kb mtp 8k instruction = 22 kb mtp or 6k intructions = 16 kb rom 8k instructions = 22 kb mtp 8k instructions = 22 kb mtp or 6k intructions = 16 kb rom 8k instructions = 22 kb mtp 8k instructions = 22 kb mtp or 6k intructions = 16 kb rom data memory 512 + 8 bytes 768 + 8 bytes 512 + 8 bytes 768 + 8 bytes 512 + 8 bytes 512 + 8 bytes port a 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt 8 input and external interrupt port b 8 input/output and analog 8 input/output and analog 8 input/output and analog 8 input/output and analog 8 input/output and analog 8 input/output and analog port c 8 input/output 8 input/output 4 to 8 input/output 4 to 8 input/output 8 input/output 8 input/output watchdog timer yes yes yes yes yes yes general purpose timers with pwm and capture 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits uart yes yes yes yes yes yes 2-3 wires serial interface transition detection + software transition detection + software transition detection + software transition detection + software transition detection + software transition detection + software voltage level detector yes yes yes yes yes yes oscillators 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc 32 khz quartz, internal rc lcd drivers 120 segments 120 segments analog mux port b and 4x2 or 7x1+1 port b and 4x2 or 7x1+1 port b port b port b and 4x2 or 7x1+1 port b lp comparators 4 4 4 pga gain 0.5 - 1000 gain 0.5 - 1000 gain 0.5 - 1000 adc 5 - 16 bits resolution 5 - 16 bits resolution 5 - 16 bits resolution dac 2 pwm 2 pwm 2 pwm 2 pwm 2 pwm 8 bit bias dac, 4 - 16 bits signal dac 2 pwm package tqfp44, die so28, tqfp32, die tqfp64, die so28, tqfp32, die availability yes samples q2/01 yes samples q2/01 yes samples q1/01 table 2.1: list of the xe8000 family members functions xx-xe88lc01/03/05, data book 3 power supply 20001101 page 19 preliminary information 3 power supply 3.1 in circuit power supply principle the power supply uses two regulators (figure 3.1), vreg should be connected to vdd for low voltage operation, vmult should be connected to vdd for high voltage operation. there are several operation modes depending on the voltage range of the power supply (figure 3.2). mtp and mixed signal blocks are limited to middle and high voltage ranges. voltage for the digital and for regular service blocks when operating in wide, middle and high voltage mode is reg- ulated below power supply to have a minimal current requirement. an additional high-voltage is generated when operating in middle voltage for controlling the internal analog switches. digital, por, oscillators figure 3.1: power supply strategy. vdd= vbat vss substrate vreg vreg continuous analog switched analog vmult level shifters vreg optional capacitor vmult optional capacitor digital, services on some models only io pad vmult figure 3.2: selection of the operation mode with respect to the power supply range. vdd (v) vss 1.2 1.4 2.4 3.3 5.5 low voltage operation wide voltage operation middle voltage operation high voltage operation 3 power supply xx-xe88lc01/03/05, data book page 20 20001101 preliminary in f ormation 3.2 voltage regulator all digital parts are powered through the voltage regulator. an external capacitor is needed for the regulated voltage. it should be bypassed to vdd if working in low voltage mode. the vreg output value depends on the program mem- ory implementation. digital, por, oscillators figure 3.3: b) power supply connection for wide voltage operation. vdd vss substrate vreg vreg level shifters vreg capacitor digital, services figure 3.3: a) power supply connection for low voltage operation. digital, por, oscillators vdd vss substrate vreg vreg level shifters digital, services digital, por, oscillators figure 3.4: power supply connection for middle voltage operation. vdd vss substrate vreg vreg continuous analog switched analog vmult level shifters vreg capacitor vmult capacitor digital, services vmult digital, por, oscillators figure 3.5: power supply connection for high voltage operation. vdd vss substrate vreg vreg continuous analog switched analog vmult level shifters vreg capacitor digital, services analog for some chips vmult xx-xe88lc01/03/05, data book 3 power supply 20001101 page 21 preliminary information 3.3 voltage multiplier the vmult block generates a voltage that is higher or equal to the supply voltage. the output voltage is intended for use in analog switch drivers, for example in the adc and pga block. the voltage multiplier should be on when using switched analog blocks, like adc, dac or analog properties of the port b under middle voltage conditions. the clock source of vmult is selected from the 2-bit register vmult_fin. the normal usage is with the clock frequency of the acquisition chain. other settings are reserved. an example of setting the regulator is as follows: move regvmultcfg0, #0b00000100; sets vmult enable bit an example of setting the regulator off follows: move regvmultcfg0, #0b00000000; resets vmult enable bit symbol description min typ max unit comments v reg regulated voltage 1.4 1.9 v t start start-up time 0.5 ms c reg external load capacitor 80 100 120 nf table 3.1: voltage regulator specifications for rom symbol description min typ max unit comments v reg regulated voltage 2 v t start start-up time tbd ms c l external load capacitor tbd nf table 3.2: voltage regulator specifications for mtp bit name reset rw description 7-3 00000 rw reserved 2 enable 0 rw 0: multiplier is stopped 1: multiplier is active 1-0 fin[1:0] 00 rw clock source for vmult: 00 : identical to acquisition chain clock (see corresponding chapter) 01 : reserved 10 : reserved 11 : reserved table 3.3: regvmultcfg0 symbol description min typ max unit comments tsu start-up time 1 ms defined as the time to reach the minimum output voltage vout cext external capacitor 1.1 1.8 2.5 nf table 3.4: vmult specifications 3 power supply xx-xe88lc01/03/05, data book page 22 20001101 preliminary in f ormation 3.4 current requirement note: 1) over 2.4 - 5.5 v, at 27 c, max values. note: 2) additional current, duration of the request is shorter than 2 ms. note: 3) output not loaded. note: 4) current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly. note: 5) at 2.4 v, at 27 c, max values. operation conditions xe88lc01r xe88lc01m xe88lc03r xe88lc03m xe88lc05r xe88lc05m remarks cpu running at 1 mips 310 ua 310 ua 310 ua 1 cpu running at 32 khz on xtal, rc off 10 ua 10 ua 10 ua 1 cpu halt, timer on xtal, rc off 1 ua 1 ua 1 ua 1 cpu halt, timer on xtal, rc ready 1.7 ua 1.7 ua 1.7 ua 1 cpu halt, xtal off timer on rc at 100 khz 1.4 ua 1.4 ua 1.4 ua 1 cpu halt, adc 12 bits at 4 khz, pga off 200 ua 200 ua 1,4 cpu halt, adc 12 bits at 4 khz, pga gain 100 480 ua 480 ua 1,4 cpu halt, lcd on, timer on xtal 1 cpu at 1 mips, adc 12 bits, signal dac 10 bits at 4 khz, pga off 725 ua 3,4,5 cpu at 1 mips, adc 12 bits, signal dac 10 bits at 4 khz, pga gain 10 870 ua 3,4,5 cpu at 1 mips, adc 12 bits, signal dac 10 bits at 4 khz, pga gain 100 1 ma 3,4,5 cpu at 1 mips, adc 12 bits, signal dac 10 bits at 4 khz, pga gain 1000 1.2 ma 3,4,5 voltage level detection 10 ua 10 ua 10 ua 2 table 3.5: current requirement of the xe8000 family members xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 23 preliminary information 4 central processing unit 4.1 introduction the xe8000 family is built around the coolrisc 816 processor core. this is a harvard type risc processor (pro- gram address is separated from data address). it is extremely efficient using large instruction words (22 bits), one clock per cycle instruction set (inclusive multiplication) and efficient pipeline. 4.1.1 pipeline the coolrisc architecture is based on a 3-stage pipeline. one instruction enters the pipeline at each clock cycle and executes in a maximum of 3 cycles. the coolrisc pipeline suffers no penalty such as delay slots or branch delays present in most risc processors. thus the clock count per instruction (cpi) is exactly one. as a result the number of cycles needed to execute a task is easily determined, since it matches the number of ex- ecuted instructions. figure 4.2 shows the timing diagram for the pipeline. arithmetic instructions go through all three stages of the pipe- line, thus executes in 3 clock cycles. a bypass mechanism is used to avoid any load delay[10]. pc <16> program memory max 64 k instructions branch address <16> 16 m u x p c 1 ip <16> p c 2..9 ir <22> op-code call to in te rrupt address control unit mux a bus <8> b bus <8> data <8> pmaddr <16> pminst <22> dataout <8> datain <8> npmsel coolrisc? core 816 16 s bus <8> regb rega c, v, z a data memory and periph max 64k bytes dmaddr <16> readnw rite dmsel register bank 8 m sb 8 lsb p c 0 +1 alu <8> mult 8*8 figure 4.1: coolrisc 816 core 4 central processing unit xx-xe88lc01/03/05, data book page 24 20001101 preliminary in f ormation it should be mentioned that existing 4-bit and 8-bit microprocessors typically need between 4 to 20 clocks per in- struction (cpi), some newer cpu use 1 clock cycle for simple operations (move) but 2 to 6 cycles for more complex operations (add, jpc). the efficiency of the coolrisc architecture is far better than these microprocessors. figure 4.2 presents the timing diagram for the execution of different types of instructions. the first instruction on figure 4.3 is a typical alu operation with a first operand in data memory (dm) and a second operand in a register. the result is stored in the destination register. during the first clock cycle, the program mem- ory (pm) is pre-charged in the first phase and the instruction is read and is decoded in the second phase. during the second clock cycle, the register and the dm are read in phase 3 and the alu operation is executed in phase 4. the last clock cycle contains only a single phase (phase 5) used to store the result in the destination register. the second instruction shown is a data memory store instruction. the first clock cycle is identical for all instructions. the second clock cycle contains only phase 3 in which the value of a register is written into the dm. exactly 1 clock cycle per instruction(cpi=1). it is not a peak value . 3-sta g e pi p eline no load/branch dela y s fetch execute write register arithmetic instructions 1 clock c y cle fetch & branch branch instructions 1 clock c y cle figure 4.2: coolrisc pipeline xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 25 preliminary information the last instruction shown is a branch instruction. a single clock cycle is necessary for all branch instructions (con- ditional or unconditional jump, call, return). during phase 2, the next program memory address can be determined while considering an already computed test condition (computed during phase 4 of the previous instruction, which is phase 2 of the considered branch instruction). the new address is loaded into the pc at the high-to-low transition of the clock between phase 2 and 3. branch instructions executed in one clock do not result in branch delays that generally degrade the pipeline perform- ance [10]. thus, cpi=1 is not a peak value, but rather a characteristic of the coolrisc? architecture. figure 4.3 shows a data memory-reg alu instruction followed by a dm store instruction. the first instruction stores its result in a register during phase 5 which is phase 3 of the dm store instruction. a bypass mechanism allows the dm store instruction to read the register that is written by the preceding alu instruction. such a mechanism does not require load delays. as the coolrisc pipeline is not affected by branch or load delays [11], the pipeline hardware is simplified (no branch prediction needs to be performed [10]). this makes the coolrisc? pipeline very efficient and low in power. 4.1.2 gated clocks the gated clock technique has been extensively used in the coolrisc? design. it uses the alu with input and con- trol registers that are loaded only when an alu operation has to be executed. during the execution of another type of instruction (branch, store, etc...), these registers are not clocked, thus no transitions occur in the alu. this reduc- es power consumption. a similar mechanism is used for the instruction registers, thus in a branch, which is executed only in the first pipeline stage, no transitions occur in the second and third stages of the pipeline. gated clocks can be advantageously combined with the pipeline architecture. when input and control registers have to be implemented to obtain a gated clock alu, they are naturally used as pipeline registers. 4.1.3 low frequency modes the processor internal frequency can be reduced by a factor of 2, 4, 8 or 16. the division factor is both hardware and software controlled. figure 4.3: pipeline execution of different instructions 4 central processing unit xx-xe88lc01/03/05, data book page 26 20001101 preliminary in f ormation the freq instruction sets the basic division factor which is output on the processor freqout[3:0] bus. this value can be combined with other signals in an external hardware decoder to compute the final division factor which is then input on the freqin[3:0] bus. power consumption can be further decreased by putting the processor in the low-power standby mode with the halt instruction. it will restart when an event or an interrupt occurs. 4.1.4 stand-by mode the halt instruction puts the processor in standby mode in which power consumption is minimum. the clock is stopped at the entrance of the processor to prevent any transition in the core. 4.1.5 coolrisc? core features 4.2 programmer's model 4.2.1 coolrisc? 816 architecture figure 4.1 shows the coolrisc? core 816 architecture which is a 8-bit microprocessor core available with 16 reg- isters and 22-bit wide instructions. 4.2.2 instruction set coolrisc? core coolrisc816 as implemented in xe88lc01-03-05 maximal coolrisc816 capabilities cpi (clock per instruction) 1 1 pipeline 3 stages 3 stages branch/load delay no no data width 8 8 no. of registers 8 16 max. program memory size 8k * 22 (= 22 kbytes) 64k * 22 (= 360 kbytes) max. data memory size 512 * 8 64k * 8 instruction size 22 22 no. of program memory index registers 1 1 no. of data memory index registers 4 4 no. of program memory pages 1 * 8k 1 * 64k no. of data memory pages 2 * 256 256 * 256 no. of data memory addressing modes 8 8 software call (branch & link) yes yes no. of nested hardware call 4 8 no. of interrupt levels 3 3 nested interrupts yes yes no. of event levels 2 2 test access serial serial halt mode yes yes 8 by 8 to 16 multiplication in one instruction yes yes barrel shifter yes yes two-complement capabilities yes yes table 4.1: coolrisc core main characteristics xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 27 preliminary information table 4.2 presents the instruction set of the coolrisc? 816. the coolrisc? provides a risc instruction set with four main categories: - branch instructions - transfer instructions - arithmetic and logic instructions - special instructions. unlike most risc microprocessors, the coolrisc? core provides instructions that can operate with operands stored either in registers or in the data memory . all arithmetic and logic instructions can be executed with a first operand in a register and a second operand either in the data memory or in a second register. the result can be stored either in a third register or in the first one. furthermore, unlike risc microprocessors and similarly to classic 8-bit microprocessors, the coolrisc? architec- ture provides an accumulator ( a ) located at the alu output. this accumulator stores the last alu result and should be used as an intermediate result for the next alu operation. this accumulator is mapped in the register bank. similarly, both the branch & link instruction of risc microprocessors (software call) and the classic hardware call are provided by the coolrisc? architecture. coolrisc? architecture can be used from the programming point of view, either as a true risc architecture or as a more classic 8-bit architecture. the coolrisc? 816, with its overflow flag ( v ) and its arithmetic instructions ( shra, cmpa, mula, mshra ) fully supports signed numbers in the two-complement representation. the mul & mula instructions execute a 8 by 8 multiplication. because the result is on 16 bits, the 8 msb bits are stored in the destination register and the 8 lsb bits are stored in the accumulator a . all the flags ( c, z, v ) must be considered as unknown after these instructions. the multiple shift instructions mshl , mshr & mshra use the multiplication instructions with an immediate oper- and. for this reason, the value of a is different from the destination register, as in the mul & mula instructions. this implies that the shifted out bits are never lost (they are either in a or in the destination register), and these instructions can be used to split a byte into two bytes, with a single instruction. for example, a swap r0 can be implemented as follows: ; r0 = 0xyz mshl r0, #4 ; r0 <- 0y, a <- z0 add r0, a ; r0 <- zy the conditional move instructions ( cmvd & cmvs ) can be used to find the maximum (or minimum) value in a table. if i0 is a pointer to the table, r0 will contain its maximum value after the following sequence: cmp(a) r0, (i0) cmvs r0, (i0)+ ; r0 <- dm(i0) if r0 < dm(i0) cmp(a)r0, (i0) cmvs r0, (i0)+ ; r0 <- dm(i0) if r0 < dm(i0) ........... 4 central processing unit xx-xe88lc01/03/05, data book page 28 20001101 preliminary in f ormation name parameters res op1 op2 function modif. jump addr:16 pc0 <- addr - , - , - , - ip pc0 <- ip jcc addr:16 if cc then pc0 <- addr ip if cc then pc0 <- ip call addr:16 pcn <- pcn-1 (n>1), pc1 <- pc0+1, pc0 <- addr ip pcn <- pcn-1 (n>1), pc1 <- pc0+1, pc0 <- ip calls addr:16 ip <- pc0+1, pc0 <- addr:16 ip ip <- pc0+1, pc0 <- ip ret pcn-1 (n>0) <- pcn - , - , - , - rets pc0 <- ip reti pcn-1 (n>0) <- pcn, gie <- 1 push pcn <- pcn-1 (n>1), pc1 <- ip, pc0 <- pc0+1 pop ip <- pc1, pcn-1 (n>1) <- pcn, pc0 <- pc0+1 move reg, data:8 reg data res <- op1 - , - , z , a reg1, reg2 reg1 reg2 reg, eaddr reg eaddr eaddr, reg eaddr reg - , - , - , - addr:8, data:8 addr data cmvd reg1, reg2 reg1 reg2 if c=0 then res <- op1 - , - , z , a cmvs reg, eaddr reg eaddr if c=1 then res <- op1 shl reg1, reg2 reg1 reg2 res(bitn) <- op1(bitn-1) (0 4 central processing unit xx-xe88lc01/03/05, data book page 30 20001101 preliminary in f ormation rflag reg reg flags <- op1, shl op1, shl a c, v, z, a eaddr eaddr freq divn:4 set cpu frequency divider -, -, -, - halt stops cpu -, -, -, - nop no operation -, -, -, - pmd s:1 if s=1 then starts program dump, if s=0 stops program dump -, -, -, - parameters data memory (dm) access index update addressing mode name eaddr addr:8 dm(addr) direct addressing (ix) dm(ix) indexed addressing (ix, offset:8) dm(ix+offset) indexed addressing with immediate offset (ix, r3) dm(ix+r3) indexed addressing with register offset (ix)+ dm(ix) ix <- ix+1 indexed addressing with post-modification of index (ix, offset:7)+ dm(ix) ix <- ix+offset -(ix) dm(ix-1) ix <- ix-1 indexed addressing with pre-modification of index -(ix, offset:7) dm(ix-offset) ix <- ix-offset table 4.3: coolrisc 816 addressing modes 11 conditions test cc cs c = 1 cc c = 0 zs z = 1 zc z = 0 vs v = 1 vc v = 0 ev (ev0 or ev1) = 1 after cmp d, s eq d = s ne d <> s gt d > s ge d >= s lt d < s le d <= s table 4.4: coolrisc 816 conditional jump (jcc) conditions information type addr:8 8-bit address addr:16 16-bit address ip program memory index ix 4 data memory (dm) indexes i0, i1, i2, i3 data:8 8-bit data offset:8 8-bit positive offset offset:7 7-bit positive offset bit:3 3-bit bit select value : 0..7 shift:3 3-bit shift value : 2..7 divn:4 0b0000: nodiv, 0b1000: div by 2, 0b1100: div by 4, 0b1110: div by 8, 0b1111: div by 16 table 4.5: coolrisc 816 instruction construction name parameters res op1 op2 function modif. table 4.2: coolrisc 816 instruction set xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 31 preliminary information the push & pop instructions allow the processor to read and write its hardware stack. this can be used to extend the depth of the stack when nested interrupts are needed. the software implementation of nested interrupts can be achieved with the following instructions : interrupt ; pc1 <- return address pop ; ip <- pc1 move eaddr1, ipl ; eaddr1 <- return. address move eaddr2, iph ; eaddr2 <- return. address ...... ; 1 stack level is now freed move ipl, eaddr1 ; ipl <- eaddr1 move iph, eaddr2 ; iph <- eaddr2 push ; pc1 <- ip ret(i) ; pc0 <- pc1 4.2.3 register bank the register bank of the 8-bit coolrisc core 816 is described in table 4.6 and table 4.7. 16 registers function reg reg1 reg2 reg3 r0 r1 r2 r3 dm offset i0l i0[7:0] i0h i0[15:8] i1l i1[7:0] i1h i1[15:8] i2l i2[7:0] i2h i2[15:8] i3l i3[7:0] i3h i3[15:8] ipl ip[7:0] iph ip[15:8] stat status a accu table 4.6: coolrisc 816 internal registers registers organization register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pc pc iph ipl ip i0h i0l i0 i1h i1l i1 i2h i2l i2 i3h i3l i3 aa r0 r0 r1 r1 r2 r2 r3 r3 ie2 ie1 gie in2 in1 in0 ev1 ev0 stat table 4.7: coolrisc 816 registers organization interrupt call address in0 3 in1 1 in2 2 table 4.8: coolrisc 816 interrupts 4 central processing unit xx-xe88lc01/03/05, data book page 32 20001101 preliminary in f ormation four data registers and an accu register are available, as well as a two-byte program memory index ( ip ) and four two-byte data memory index ( ix ) registers. these index registers allow the user to address up to 64k instructions and up to 64k data bytes. ip is also used to save the return address with the software call instruction ( calls ). a status register ( stat ) is used only to control interrupts and events. r3 can also be used as an offset register in the indexed addressing mode of the data memory. if some of the 10 data & program memory index registers are not used permanently as indexes, they can be used as data registers. furthermore, if some of them are not used in a given routine, they can also be advantageously used as temporary data registers. table 4.9 summarises the names and the roles of the registers. 4.2.4 program memory addressing modes the coolrisc 816 provides one 16-bit program memory index called ip in order to address indirectly the 64k of program memory ( ipl for the lsb bits, iph for the msb). the address field in a direct jump instruction is of 16 bits. this allows addressing directly to the whole program memory space. 4.2.5 data memory addressing modes the coolrisc? 816 provides four 16-bit data memory indexes called ix ( i0, i1, i2 & i3) in order to address 64k bytes of data memory ( ixl for the lsb bits, ixh for the msb). the data memory is organised as 256 pages of 256 bytes. the whole memory can be addressed indirectly using ix, while only page 0 can be addressed directly. 4.2.5.1 direct addressing data memory access : dm(addr:8) register names data regs data mem. index prog. mem. index soft. call ax r0 x r1 x r2 x r3 x dm offset i0l x x i0h x x i1l x x i1h x x i2l x x i2h x x i3l x x i3h x x ipl x x x iph x x x stat table 4.9: registers roles xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 33 preliminary information this mode is limited to the addressing of page 0. the field addr:8 of the corresponding instructions is used as a direct address (dmaddr[7:0]) while the msb bits of the data memory address (dmaddr[15:8]) are equal to 0. 4.2.5.2 indexed addressing data memory access : dm(ix) the complete data memory space can be addressed with this mode. the value of the index ix is the data memory address (dmaddr[15:0]). the 8 lsb bits ( ixl ) define the offset in the page while the 8 msb bits ( ixh ) define the page number. therefore 256 pages of 256 bytes can be addressed. 4.2.5.3 indexed addressing with an immediate offset data memory access : dm(ix+offset:8) m u x m u x offset [7:0] r3 +/- dmaddr [ 15:8 ] 0 dmaddr [ 7:0 ] addr [ 7:0 ] m u x m u x direct addressin g m u x i0 i1 i2 i3 8 16 8 8 16 16 figure 4.4: direct addressing m u x m u x offset [7:0] r3 +/- dmaddr [ 15:8 ] 0 dmaddr [ 7:0 ] addr[7:0] m u x m u x direct addressin g m u x i0 i1 i2 i3 8 16 8 8 16 16 figure 4.5: indexed addressing 4 central processing unit xx-xe88lc01/03/05, data book page 34 20001101 preliminary in f ormation the 16-bit data memory address dmaddr[15:0] is calculated by the addition of an 8-bit positive offset:8 taken in the instruction to one of the 16-bit index ix . 4.2.5.4 indexed addressing with a register offset data memory access : dm(ix+r3) the 16-bit data memory address dmaddr[15:0] is calculated by the addition of the 8-bit positive value of the r3 register to one of the 16-bit index ix . 4.2.5.5 indexed addressing with post-modification of the index data memory access : dm(ix) m u x m u x offset [ 7:0 ] r3 + dmaddr [ 15:8 ] 0 dmaddr [ 7:0 ] addr[7:0] m u x m u x direct addressin g m u x i0 i1 i2 i3 8 16 8 8 16 16 figure 4.6: indexed addressing with an immediate offset m u x m u x offset [7:0] r3 + dmaddr [ 15:8 ] 0 dmaddr [ 7:0 ] addr[7:0] m u x m u x direct addressin g m u x i0 i1 i2 i3 8 16 8 8 16 16 figure 4.7: indexed addressing with a register offset xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 35 preliminary information index update : ix <- ix+offset:7 particular case : offset:7 = 1 the 16-bit data memory address dmaddr[15:0] is given directly by the value of one of the 16-bit index ix . the 16- bit index ix is updated by the addition of the 7-bit positive offset:7 field in the corresponding instruction. 4.2.5.6 indexed addressing with pre-modification of the index data memory access : dm(ix-offset:7) index update : ix <- ix-offset:7 particular case : offset:7 = 1 the 16-bit data memory address dmaddr[15:0] is calculated by the subtraction of the 7-bit positive offset:7 from the 16-bit index ix . the 16-bit index ix is updated by the subtraction of the 7-bit positive offset:7 field in the corre- sponding instruction. m u x m u x offset [ 6:0 ] r3 + dmaddr [ 15:8 ] 0 dmaddr [ 7:0 ] addr[7:0] m u x m u x direct addressin g m u x i0 i1 i2 i3 7 16 8 8 16 16 figure 4.8: indexed addressing with post-modification of the index m u x m u x offset [ 6:0 ] r3 - dmaddr [ 15:8 ] 0 dmaddr [ 7:0 ] addr[7:0] m u x m u x direct addressin g m u x i0 i1 i2 i3 7 16 8 8 16 16 figure 4.9: indexed addressing with pre-modification of the index 4 central processing unit xx-xe88lc01/03/05, data book page 36 20001101 preliminary in f ormation 4.2.5.7 remark on the indexed addressing in an indexed data memory access, the index used for the access may also be used as the destination register for the operation. in the case of pre/post index modification, the index ix is updated before the result of the operation is stored in ixl or ixh . 4.2.6 flags z, c & v the flag z (zero) is modified by all alu operations (including the move into a register). z = 1 only if the alu output (not the multiplier output ) is equal to 0. the flags c (carry) and v (overflow) are only modified by arithmetic, comparison and shift operations. in shift operations, c always contains the shifted out bit. in arithmetic operations with unsigned numbers, c indicates whether an overflow or an underflow occurs (can be active either high or low depending on the operation). in arithmetic and shift operations with signed numbers, v indicates whether an overflow or an underflow occurs. v = 1 when overflow (or underflow). after the comparison instructions cmp(a) d, s : c = 0 if d > s and v = c * not( z) 4.2.7 alu output register: a the alu output register (figure 2.1) named a always contains the result of the last alu operation. it is a temporary register that is always modified by alu operations. it is addressed as a normal register in the register bank. it should be used for temporary results, as power-consump- tion is saved if this low-power accumulator is used instead of another data register. 4.2.8 program counter the 16-bit program counter (pc) can address a program memory with up to 64k instructions. a hardware stack is provided for efficient subroutine and interrupt support. when the hardware stack is full, interrupt is disabled until one level of the stack becomes free again (ret or reti). additional subroutine levels are supported with no hardware cost through the use of the software call mechanism (calls instruction). 4.2.9 branch conditions after a comparison instruction ( cmp ), 6 conditional branch instructions are possible depending on the comparison result, after the other alu operations, 6 conditional branch instructions are possible depending on the value of the flags. the jev branch instruction is executed if one (or more) of the event bits of the status register is active (equal to 1). xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 37 preliminary information the carry ( c ), the overflow ( v ) and the zero ( z ) flags result from the "previous" alu operation (which modified the flags!). table 4.10 summarises the different branch conditions available. the branch jev is executed if one (or more) of the event bits of the status register is active (equal to 1). 4.2.10 call, branch and link in most risc microprocessors, only a branch & link mechanism is available. this mechanism saves the return ad- dress in a register. the programmer is responsible to save this address in the data memory before a new software call is used. coolrisc provides both hardware and software call mechanisms. the software call stores the return address in a particular register which is the two-byte program memory index ip . therefore, the programmer has to save ip (if it is used) before a software call ( calls ). 4.2.11 events and interrupts the 8-bit status register ( stat ) contains the following booleans: bit0: event nb 0 ( ev0 ) bit1: event nb 1 ( ev1 ) bit2: interrupt nb 0 ( in0 ) bit3: interrupt nb 1 ( in1 ) bit4: interrupt nb 2 ( in2 ) bit5: enable bit for all interrupts ( gie ) bit6: enable bit for in1 ( ie1 ) bit7: enable bit for in2 ( ie2 ) events and interrupts are boolean flags which can be either hardware or software modified. a negative pulse on one of the nevent[1:0] or ninterrupt[2:0] pins will set the corresponding bit to 1. in addition, a write to the status register can either set or reset any of these bits. therefore interrupts and events can be forced by software (see next chapter: pipeline exception). note however that a is modified when software interrupt are generated (by an alu operation). interrupts force a call to a fixed address (one specific address for each interrupt), save the program counter (pc) on the stack (which will be restored by the reti or ret instruction), and start the processor if it is in the halt mode. branch test branch on alu result jcs c = 1 jcc c = 0 jvs v = 1 jvc v = 0 jzs z = 1 jzc z = 0 branch on event jev (ev0 or ev1) = 1 branch on cmp result jeq d = s jne d <> s jgt d > s jge d >= s jlt d < s jle d <= s table 4.10: branch conditions 4 central processing unit xx-xe88lc01/03/05, data book page 38 20001101 preliminary in f ormation the designer must save the accumulator a , the flag c and the working registers (which are used in the interrupt routine) at the beginning of the interrupt routine, and restore them at the end as follows : move eaddr1, a ;save a & z sflag ;a ( c & v move eaddr2, a ;save c & v move eaddr3, ri ;save ri .......................... move ri, eaddr3 ;restore ri rflag eaddr2 ;restore c & v move a, eaddr1 ;restore a & z a disabled interrupt (corresponding enable bit at 0) cannot force a call, and cannot start the cpu if it is in the halt mode. however, the request is taken into account and will be executed as soon as the corresponding enable bit is set to 1, unless the interrupt bit has been successfully cleared by software in the meantime. the general interrupt enable bit gie ( stat[5] ), if 0, disables any interrupt with the same principle as above. when a call to an interrupt routine is executed, gie is automatically cleared in order to prevent the cpu executing another call to the same (or another) interrupt. when the reti instruction is executed, gie is automatically set to 1 in order to allow interrupts to occur again. in order to return from an interrupt, ret must be used instead of reti if the programmer does not want to change the value of gie . the programmer may allow nested interrupts by setting gie to 1. but each time a new call to an interrupt is exe- cuted, a new level of the hardware stack is used. when the hardware stack is full, interrupts are disabled independently of the value of gie . as soon as a level of the stack is freed ( ret , reti ), a pending interrupt can be executed. an action on the nevent[1:0] pins restarts the processor if it is in the halt mode. in contrast to the interrupt, an event does not force a call to a predefined address. it should be used as a handshake facility. the halt instruction is only effective if all event bits and all non-masked interrupt bits are cleared. the nevent and ninterrupt lines are active low, but a "short" negative pulse is sufficient to set the event or interrupt bit in the status register. clearing an event or an interrupt bit is only possible if the corresponding input line is not active. this allows the ex- ecution of an interrupt routine as long as the corresponding input line is active. in the interrupt routine, it is recommended first to desactivate the interrupt line (by commanding the corresponding peripheral to release the line), and then to clear the corresponding interrupt bit. thus, it will be possible to receive a new interrupt (on the same input) as soon as the interrupt bit is cleared. if several interrupts are pending, they are executed in order of priority. only gie is reset by a hardware reset. the other booleans must be initialised by the programmer. table 4.11 shows the call addresses and the priorities of the interrupts. inter. nb. call ad. priority inter. nb 0 3 highest inter. nb 1 1 medium table 4.11: call addresses and priorities xx-xe88lc01/03/05, data book 4 central processing unit 20001101 page 39 preliminary information 4.2.12 pipeline exception if an interrupt bit is set by the software (write into stat ) the pipeline causes the next instruction to be executed "be- fore" the cpu executes the interrupt routine. this allows to supply a parameter to a trap as follows : setb stat, #4 ; trap move a, #parameter ; a ( parameter if an event bit is set by software, and a "jump on event" ( jev ) is the next instruction, the first instruction will be ignored by the second. these are the only delays caused by the coolrisc? pipeline. 4.2.13 halt mode the halt instruction turns the processor into stand-by mode, in which power consumption is minimum. only an event, an interrupt or a hardware reset are able to wake up the microprocessor. the halt instruction is only effective if all event bits and all enabled interrupt bits are inactive (low). when the processor stops because of a halt instruction, the previous instruction is totally executed before the stand-by mode occurs. the next instruction will only begin when the processor restarts. 4.2.14 hardware reset when the nreset signal goes low, the general interrupt mask bit gie is reset, the cpu restarts if it was in the halt mode, the frequency division factor is set to 1x, the pc stack is emptied, and the test mode is reset as well as the program memory dump mode. furthermore, at each rising edge of the external clock, a jump to address 0 is forced. the instruction located at address 0 will be executed when the nreset signal returns high. 4.2.15 low frequency modes as explained in chapter 1.6, the processor internal frequency can be reduced by a factor of 2, 4, 8 or 16. the division factor is both hardware and software controlled. the freq instruction sets the basic division factor which is output on the freqout[3:0] bus. the instruction that follows freq is already executed with the new processor frequency. inter. nb 2 2 lowest inter. nb. call ad. priority table 4.11: call addresses and priorities 4 central processing unit xx-xe88lc01/03/05, data book page 40 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 5 memory 20001101 page 41 preliminary information 5memory 5.1 memory organisation the mcu uses a harvard architecture, so that memory is organised in two separated fields: program memory and data memory. as the memory is separated, the central processing unit can read/write data at the same time it loads an instruction. peripherals and system control registers are mapped on data memory space. program memory is made in one page (program address bus is 16 bits wide). data is made of several 256 bytes pages. 5.2 program memory the program memory is implemented as multiple time programmable (mtp) flash memory or read-only memory (rom). the power consumption of mtp and rom is linear with the access frequency (no static current). memory sizes : ? flash mtp: 8192 x 22 bits ? rom : 8192 x 22 bits 5.3 data memory the data memory is implemented as static random-access memory (ram). the ram size is 512 x 8 bits, plus a 8 x 8 low memory registers (named lp ram) that require very low current when addressed. programs using these registers instead of regular ram will spare current. note: the ram content is not defined at power-up. note: the registers in data memory (lp ram) are not related to the cpu registers. block size address rom/mtp 8192 x 22 h0000 - h1fff table 5.1: program addresses figure 5.1: memory organization cpu program memory lp ram peripherals ram program address bus data address bus 22 bits wide 8 bits wide cpu registers instruction pipeline 5 memory xx-xe88lc01/03/05, data book page 42 20001101 preliminary in f ormation 5.4 peripherals mapping 5.5 address pack a standardized peripheral address naming is provided to help developpers. the address pack is shown in xemics application note an8000.01. 5.6 mtp flash memory programmation 5.6.1 introduction the programmation process uses the test interface of the cpu (the main clock of the processor, and its testin, tes- tout and testck ports), a reset port (active high) and another clock (ptck). it requires that the xe88lc01/03/05 is in test mode (test/vpp above vdd), connecting internal signals to pins. more detailed information is given in xemics application note an8000.02. be aware that the xe88lc02/04/06 and above use another programming algorithm. block size address lp ram 8 x 8 h0000 - h0007 ram 512 x 8 h0080 - h027f table 5.2: ram addresses block size address page specific chapter lp ram 8x8 h0000-h0007 page 0 memory on page 41 (low power memory) reserved 8x8 h0008-h000f system control 16x8 h0010-h001f system operating modes on page 45 port a 8x8 h0020-h0027 parallel io ports on page 67 port b 8x8 h0028-h002f port c 4x8 h0030-h0033 port d 4x8 h0034-h0037 mtp 4x8 h0038-h003b memory on page 41 (used only for mtp programming) event 4x8 h003c-h003f system operating modes on page 45 interrupts control 8x8 h0040-h0047 usrt 8x8 h0048-h004f universal synchronous receiver/transmitter (usrt) on page 83 uart 8x8 h0050-h0057 universal asynchronous receiver/transmitter (uart) on page 77 counters 8x8 h0058-h005f counters/timers on page 85 adc 8x8 h0060-h0067 acquisition chain on page 101 reserved 12x8 h0068-h0073 dacs 8x8 h0074-h007b analog outputs on page 109 other (vmult, vld) 4x8 h007c-h007f power supply on page 19 and voltage level detector on page 97 ram1 128x8 h0080 - h00ff ram2 256x8 h0100 - h01ff page 1 ram3 128x8 h0200 - h027f page 2 table 5.3: peripherals addresses xx-xe88lc01/03/05, data book 5 memory 20001101 page 43 preliminary information 5.6.2 mtp registers register name address regeep h0038 regeep1 h0039 regeep2 h003a regeep3 h003b table 5.4: mtp registers figure 5.2: mtp registers organisation regeep regeep1 regeep2msb regeep3msb regeep3mid regeep3lsb regeep2lsb address bus data bus mtp memory address instruction 16 8 16 22 5 memory xx-xe88lc01/03/05, data book page 44 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 45 preliminary information 6 system operating modes the system block controls resets, interrupts, events, clocks and operating modes. 6.1 operating modes the xe8000 system can operate in three different modes from which two are low-power dissipation modes (standby and sleep). in addition to that, most peripherals also have several low power modes. ? active mode (normal operation) ? standby mode (cpu halt, oscillator on) ? sleep mode (oscillator off, ram state maintained) 6.1.1 start-up and reset states these states can only be entered following reset (see figure 6.3). a correct start-up of the whole microcontroller is ensured. 6.1.2 active mode this is the running mode where all peripherals can work and the cpu executes instructions. 6.1.3 standby mode executing a halt instruction puts the xe8000 into the standby mode. the voltage regulators, oscillators, watch- dog timer, interrupts, events and counters can be operated. however, the cpu stops, since the clock related to instruction fetching and execution stops. registers, ram, and i/o pins retain their states prior to standby mode. standby is cancelled by a reset (except buserror reset) or an interrupt/event request if enabled. note: unless disabled, watchdog timer is running in standby mode. cpu clock selection figure 6.1: system block rc xtal resetcold resetpad resetsys clearpre clearwd bitsleep ckrc ckxtal addr decoder xtal cold start bitcoldrc bitcoldxtal rc cold start external clock bitextclk resetsleep sleep mode ckcpu cpu reset pin por buserror porta resetporta reset sources/ synchronize watchdog resetwd clocks ck1 all signals enter left, top or bottom and output right of the boxes. ck1 xtalpower xtalpower rcpower rcpower peripherals ck125 resetwd prescaler 6 system operating modes xx-xe88lc01/03/05, data book page 46 20001101 preliminary in f ormation 6.1.4 sleep mode this is a very low-power mode in which all peripherals are stopped. all internal registers and ram keep the value before sleep mode. this mode can be used when no time-keeping is necessary. both oscillators are stopped. to put the xe8000 in sleep mode first the sleepen (sleep enable) bit in regsysctrl must be set to 1. the only reset which clears this bit is the power-on-reset. it can be cleared at any time also by writing 0 to this location. once the sleepen bit is set to one, writing the sleep bit in regsysreset immediately puts the xe8000 in the sleep mode. there are only three possible ways to wake-up from the sleep mode : 1. in case of power-down followed by power-on, the power-on-reset initializes the whole system. in this case, the peripheral register contents and the ram information is lost. 2. reset pad, no information loss. 3. porta reset combination, no information loss. if the reset pin or porta reset is the wake-up condition, the sleepen bit is not cleared and this therefore provides the information that the circuit was previously running and that the xe8000 should now wake up from sleep mode. note: due to the pipelined architecture, the instruction following the writing of the sleep bit may be executed un- der certain conditions. therefore, the writing of the sleep bit must be followed by a nop. note: watchdog timer is stopped in sleep mode. figure 6.2: sleep mode structure bitensleep bitsleep_tmp ck_regsysctrl datain[7] ck_regsysclock ckcpu bitsleep resetcold resetporta resetpad datain[7] to cpu xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 47 preliminary information 6.2 resets to initialize the xe8000, a system reset must be executed. register name address (hex) comments regsysctrl h0010 system sleep and reset flags regsysreset h0011 system sleep and reset enable regsysclock h0012 clock selection regsysmisc h0013 special functions regsyswd h0014 watchdog regsyspre0 h0015 prescaler regsyspre1 h0016 regsystest1 h0017 reserved regsystest2 h0018 regsystest3 h0019 regsystestana h001a regsysrctrim1 h001b rc clock frequency select regsysrctrim2 h001c regsysvireg h001d internal regulator setting - h001e reserved regsyswarm h001f reserved table 6.1: system registers figure 6.3: system operating modes. most peripherals also have several low power modes low current ultra low current no activity sleep rc off rc bias on or off xtal off stand-by cpu halted clocks active active cpu active clocks active reset cpu halted clocks active padreset porta reset watchdog reset buserror reset padreset porta reset watchdog reset halt instruction interrupt / event por padreset porta reset set bit sleep after 4 cpu clock cycles start-up start phase rc on xtal off por after 8 rc clock cycles por por active time keeping memory keeping 6 system operating modes xx-xe88lc01/03/05, data book page 48 20001101 preliminary in f ormation this can be performed in 5 ways: ? initial reset from the power-on reset (por) ? external reset from the reset pin ? port a reset combination (programmable) ? watchdog timer reset (programmable enable) ? wrong data memory address reset = buserror reset power-on reset is treated as a special case with an additional coldstart delay on rc oscillator. this coldstart delay guarantees a stable oscillator clock once it is finished (see figure 6.3). the circuit always starts with the rc oscillator because its start-up time is very short compared to the quartz oscillator. once the rc coldstart delay of several rc clock is finished, the oscillator selector detecting only the rc clock needs an additional rc period to switch to rc oscillator for system clock. from now on all reset sources go via the reset synchronizer logic which prolongs any reset by 3 whole system clock periods and then releases the system reset on the falling edge of the system clock. the program counter for instruction words is cleared to 0 and first jump main instruction is executed after the end of system reset. rc ck figure 6.4: power-on reset start cpu ck 1234 . . . 5-10 ms. .. system reset coldstartrc cpuaddr ..... por vdd 0000 main rc ck figure 6.5: wake from sleep (short reset) cpu ck 12345678910 system reset coldstartrc cpuaddr 11 12 13 14 15 reset source 0000 main ???? rc ck figure 6.6: wake from sleep (long reset) cpu ck 12345678910 system reset coldstartrc cpuaddr 11 12 13 14 15 reset source 0000 main ???? xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 49 preliminary information 6.2.1 initial reset from the power-on-circuit at power-on the por circuit supplied by the internal voltage regulator (which also supplies the whole digital part ) generates a reset until the regulated voltage is high enough for the ic to work. 6.2.2 external reset from the reset pin system reset can be activated by using the reset pin. 6.2.3 porta programmed reset combination. as described in the porta description a porta reset can be programmed. when input porta status matches the pro- grammed combination in regpares0 and regpares1 a reset is generated which lasts until reset porta status is removed from porta inputs. direct non-debounced porta status is used for this reset. 6.2.4 watch-dog timer reset the watchdog timer will generate a reset if it is not cleared on time. see chapter watchdog timer for details. 6.2.5 buserror reset address space is distributed as shown in register mapping to different peripherals. if an unused address region was addressed, then the buserror reset is executed. 6.2.6 reset registers two registers are dedicated for reset status and control, regsysreset and regsysctrl . the bits sleep and sleep- en are also located in those registers but have nothing to do with reset and are described in a dedicated chapter. regsysreset gives reset source information. ? resbuserror an undefined peripheral register was addressed. ? reswd the watchdog timer generated a reset. ? resporta a porta combination generated a reset. ? respad reset pad was used . ? respadsleep reset pad was used during sleep mode. regsysctrl enables reset sources ? enbuserror enables reset source from bus error ? enreswd enables reset source from watchdog ? enrespconf has a special function. it is a reset source selection for port configuration reset. it can be acti- vated either with power-on reset only or with a combination of power-on reset and any other reset source. enrespconf resetpconf 1 any reset source 0 por only table 6.2: enrespconf cpuck figure 6.7: reset in active mode system reset coldstartrc/xtal cpuaddr reset source 0000 main ???? ???? ???? ???? 6 system operating modes xx-xe88lc01/03/05, data book page 50 20001101 preliminary in f ormation 6.2.7 oscillators and prescaler control this is described in the oscillators chapter. 6.2.8 other features ? rconpa0 if set to one, an event (or interrupt) on pad pa[0] will start the rc oscillator by setting ena- blerc ? debfast debouncer clock selection. this clock is used for all digital debouncer in the xe8000 ? outputckxtal output xtal clock on portpb[3] ? outputckcpu output cpuckout clock on portpb[2]. 6.3 interrupt 6.3.1 features the xe8000 support 16 interrupt sources, namely: bit name reset rw description 7sleep resetpor or resetporta or resetpad or resetcold w sleep flag (read value is 0) 6 respor 0 r t por status in test mode 5 resbuserror 0 resetcold r c reset source is buserror 4 reswd 0 resetcold r c reset source is watchdog 3 resporta 0 resetcold r c reset source is porta combination 2 respad 0 resetcold r c reset source is debounced pad reset 1 respadsleep 0 resetcold r c reset source is pad reset (in sleep mode) 0 0 r reserved table 6.3: regsysreset bit name reset rw description 7 sleepen 0 resetpor r w enable sleep flag 6 enrespconf 0 resetcold rw enable reset port config when resetsystem 5 enbuserror 0 resetcold rw enable reset from buserror 4 enreswd 0 resetcold rw enable reset from watchdog this bit can not be set to 0 by software 3-0 -- 0000 r unused table 6.4: regsysctrl debfast debouncer frequency 18khz 0256hz table 6.5: debouncer frequency bit name reset rw description 7 disrespad 0 testpad r wt disable resetpad in test mode 6-4 -- 000 r unused 3 rconpa0 0 resetsleep r w start rc on pa[0] 2 debfast 0 resetsleep r w debouncer clock speed (0=slow) 1 outputckxtal 0 resetsleep r w output ckxtal on pad pb[3] 0 outputckcpu 0 resetsleep r w output ckoutcpu on pad pb[2] table 6.6: regsysmisc xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 51 preliminary information ? 8 external inputs from porta ? 4 from the internal counters a,b,c and d ? 2 from the internal prescaler (128hz and 1hz ) ? 1 from internal voltage level detector ? 1 from acquisition chain these interrupts have 3 levels of priority. 6.3.2 overview the interrupts are divided into 3 categories with different priorities. the priorities are fixed and are described below : ? high: acquisition chain, countera, counterc, prescaler 128hz, uarttx, uartrx ? mid: porta[0,1,4,5], prescaler 1hz, vld ? low: porta[2,3,6,7], counterb, counterd. there is an interrupt flag register associated with each priority. the interrupt flag registers are regirqhig , regir- qmid and regirqlow . the rising edge of the interrupt (irq) source sets the interrupt flag if it is enabled. the interrupt flag is automatically cleared following system resets and can be cleared by software. this is achieved by writing the corresponding flag in the regirqxxx register to 1. for definitively clearing the interrupt, one has to disable the corresponding bit in the coolrisc status register . for example if an interrupt is generated by the pad 0 of port a: move regirqmid, #0x01 clrb stat,#3 each interrupt (irq) source can be enabled or disabled by software with the help of the interrupt enable registers regirqenhig , regirqenmid and regirqenlow . there is a bit within each of these registers corresponding to the list above. for example, within regirqenhig , there is a bit corresponding to each of countera, counterc, prescaler 128hz, uarttx and uartrx that enables/disables the associated interrupt accordingly. 6.3.3 porta interrupts it is possible to use each pin of porta (8 pins) as an independent edge triggered irq input. bitwise configuration (debounced or non-debounced / falling or rising edge) is performed using reserved registers in porta. the debouncer frequency can be either 256hz (slow debouncer clock) or 8khz (fast-debouncer clock). the de- bounce clock is common for all 8 porta inputs (and also for the reset pad). when debounced, the signal on porta has to be stable for one to two periods of selected internal debounce clock to ensure that the new logical value is accepted. 6.3.4 counters a, b, c and d interrupts counters generate interrupts only when they work as normal counters (as opposed to pwms). loops counters generate interrupts regularly, depending on their mode of operation (up/down counting). if more in- terrupts arrive from the same counter before its interrupt is served, second and subsequent interrupts are ignored. this can be the case when interrupts arrive too quickly or the interrupt service routine is currently serving some high- er priority interrupts. 6.3.5 prescaler interrupts two interrupts are available from the prescaler, 128hz and 1hz. both are generated by the low 15-stage divider.this means that they can be accurate at 128hz and 1hz only when the xtal 32768 quartz oscillator is enabled. if the xtal is not enabled, they are derived from the rc oscillator fre- quency. the prescaler can be resynchronized at any time by resetting it. 6 system operating modes xx-xe88lc01/03/05, data book page 52 20001101 preliminary in f ormation 6.3.6 voltage level detector interrupt the voltage level detector generates an interrupt following supply voltage comparison in response to a comparison request. the interrupt indicates the comparison is complete. 6.3.7 acquisition chain interrupt the acquisition chain generates an interrupt when the acquisition is completed. 6.3.8 interrupt priorities two registers have been provided to facilitate the writing of interrupt service software namely : ? regirqpriority ? regirqirq the first, regirqpriority, contains the id-code of the highest priority interrupt. the table below shows these priori- ties which correspond to organization of interrupts in the registers above and their id-code. id-codes h15, h12, h11, h10, h1, and h0 are not used in this product. code h17 is only used in some products. after any system reset the regirqpriority value is hff indicating no interrupt request has been issued subse- quently to the reset. the second, regirqirq, indicates the priority levels of the current irqs. the three levels of interrupts map directly to those supported by the coolrisc (in0, in1 & in2). for more information, see the documentation about the coolrisc816 core. regirqpriority irq on cpu (priority) highest priority interrupt set hff none no interrupt h17 in0 (high) irqac h16 in0 (high) irqpre1 h14 in0 (high) irqcnta h13 in0 (high) irqcntc h11 in0 (high) irquarttx h10 in0 (high) irquartrx h0f in1 (mid) reserved h0e in1 (mid) reserved h0d in1 (mid) irqpa[5] h0c in1 (mid) irqpa[4] h0b in1 (mid) iirqpre2 h0a in1 (mid) irqvld h09 in1 (mid) irqpa[1] h08 in1 (mid) irqpa[0] h07 in2 (low) irqpa[7] h06 in2 (low) irqpa[6] h05 in2 (low) irqcntb h04 in2 (low) irqcntd h03 in2 (low) irqpa[3] h02 in2 (low) irqpa[2] table 6.7: all interrupts and their priorities register name address (hex) regirqhig h0040 table 6.8: interrupt registers xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 53 preliminary information regirqmid h0041 regirqlow h0042 regirqenhig h0043 regirqenmid h0044 regirqenlow h0045 regirqpriority h0046 regirqirq h0047 bit name reset rw description 7 irqac 0 resetsystem r c1 interrupt from acquisition chain (when available) 6 irqpre1 0 resetsystem r c1 interrupt from prescaler (128 hz) 5 -- 0 r unused 4 irqcnta 0 resetsystem r c1 interrupt from countera 3 irqcntc 0 resetsystem r c1 interrupt from counterc 2 -- 0 r unused 1 irquarttx 0 resetsystem r c1 interrupt from uart transmitter 0 irquartrx 0 resetsystem r c1 interrupt from uart receiver table 6.9: regirqhig bit name reset rw description 7 reserved 0 resetsystem r c1 6 reserved 0 resetsystem r c1 5 irqpa[5] 0 resetsystem r c1 interrupt from pad pa[5] 4 irqpa[4] 0 resetsystem r c1 interrupt from pad pa[4] 3 irqpre2 0 resetsystem r c1 interrupt from prescaler (1 hz) 2 irqvld 0 resetsystem r c1 interrupt from voltage level detector 1 irqpa[1] 0 resetsystem r c1 interrupt form pad pa[1] 0 irqpa[0] 0 resetsystem r c1 interrupt form pad pa[0] table 6.10: regirqmid bit name reset rw description 7 irqpa[7] 0 resetsystem r c1 interrupt from pad pa[7] 6 irqpa[6] 0 resetsystem r c1 interrupt from pad pa[6] 5 irqcntb 0 resetsystem r c1 interrupt from counterb 4 irqcntd 0 resetsystem r c1 interrupt from counterd 3 irqpa[3] 0 resetsystem r c1 interrupt from pad pa[3] 2 irqpa[2] 0 resetsystem r c1 interrupt from pad pa[2] 1 -- 0 r unused 0 -- 0 r unused table 6.11: regirqlow bit name reset rw description 7 irqenac 0 resetsystem r w enable interrupt from acquisition chain (when available) 6 irqenpre1 0 resetsystem r w enable interrupt from prescaler (128 hz) 5 -- 0 r unused 4 irqencnta 0 resetsystem r w enable interrupt from countera 3 irqencntc 0 resetsystem r w enable interrupt from counterc 2 -- 0 r unused 1 irqenuarttx 0 resetsystem r w enable interrupt from uart transmitter 0 irqenuartrx 0 resetsystem r w enable interrupt from uart receiver table 6.12: regirqenhig register name address (hex) table 6.8: interrupt registers 6 system operating modes xx-xe88lc01/03/05, data book page 54 20001101 preliminary in f ormation 6.4 events 6.4.1 features the xe8000 support 8 event sources, namely: ? 2 external inputs from porta ? 4 from the internal counters a,b,c and d ? 2 from the internal prescaler (128hz and 1hz ) events are used to restart the cpu after a halt instruction, without having to handle a complete interrupt cycle. these events display 2 levels of priority. bit name reset rw description 7 reserved 0 resetsystem r w bit should not be used 6 reserved 0 resetsystem r w bit should not be used 5 irqenpa[5] 0 resetsystem r w enable interrupt from pad pa[5] 4 irqenpa[4] 0 resetsystem r w enable interrupt from pad pa[4] 3 irqenpre2 0 resetsystem r w enable interrupt from prescaler (1 hz) 2 irqenvld 0 resetsystem r w enable interrupt from voltage level detector 1 irqenpa[1] 0 resetsystem r w enable interrupt from pad pa[1] 0 irqenpa[0] 0 resetsystem r w enable interrupt from pad pa[0] table 6.13: regirqenmid bit name reset rw description 7 irqenpa[7] 0 resetsystem r w enable interrupt from pad pa[7] 6 irqenpa[6] 0 resetsystem r w enable interrupt from pad pa[6] 5 irqencntb 0 resetsystem r w enable interrupt from counterb 4 irqencntd 0 resetsystem r w enable interrupt from counterd 3 irqenpa[3] 0 resetsystem r w enable interrupt from pad pa[3] 2 irqenpa[2] 0 resetsystem r w enable interrupt from pad pa[2] 1 -- 0 r unused 0 -- 0 r unused table 6.14: regirqenlow bit name reset rw description 7-0 irqpriority hff resetsystem r code of highest priority set interrupt table 6.15: regirqpriority bit name reset rw description 7-3 -- 0 r unused 2 irqhig 0 resetsystem r one (or more) high priority interrupt is set 1 irqmid 0 resetsystem r one (or more) middle priority interrupt is set 0 irqlow 0 resetsystem r one (or more) low priority interrupt is set table 6.16: regirqirq bit name reset rw description 7-0 irqtest 00000000 resetsystem wt for test only table 6.17: regirqtest xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 55 preliminary information 6.4.2 overview the events are divided into 2 categories with different priorities. the priorities are fixed and are described below : ? high: countera, counterc, prescaler 128hz & pad pa[1] ? low: counterb, counterd, prescaler 1hz & pad pa[0] there is an event flag register associated with each priority. the event flag register is regevn . the rising edge of the event (evn) source sets the event flag if it is enabled. the event flag is automatically cleared following system resets and can be cleared by software. this is achieved by writing the corresponding flag in the regevn register to 1 (the coolrisc events are active low). for clearing definitively the event, one has to disable the corresponding bit in the coolrisc status register. for example if a event is generated by the pad 0 of port a: move regevn, #0x01 clrb stat,#1 each event (evn) source can be enabled or disabled by software with the help of the event enable registers re- gevnen . 6.4.3 porta events it is possible to use pin pa[0] & pa[1] of porta as an independent edge triggered evn input. bitwise configuration (debounced or non-debounced / falling or rising edge) is performed using reserved registers in porta. the debouncer frequency can be either 256hz (slow debouncer clock) or 8khz (fast-debouncer clock). the de- bounce clock is common for all 8 porta inputs (and also for the reset pad). when debounced, the signal on porta has to be stable for one to two periods of selected internal debounce clock to ensure that the new logical value is accepted. 6.4.4 counters a, b, c and d events counters generate events only when they work as normal counters (not when set to pwm). loop counters generate events regularly, depending on their mode of operation (up/down counting). it is for the soft- ware programmer to handle the processing of events. 6.4.5 prescaler events two events are available from the prescaler, 128hz and 1hz. both are generated by the low 15-stage divider.this means that they can be accurate at 128hz and 1hz only when the xtal 32768 quartz oscillator is enabled. if the xtal is not enabled, they are derived from the rc oscillator fre- quency. the prescaler can be resynchronized at any time by resetting it. 6.4.6 event priorities two registers have been provided to facilitate the writing of software used for handling events, namely : ? regevnpriority ? regevnevn the first, regevnpriority, contains the id-code of the highest activated priority event. the table below shows these priorities which correspond to organization of event in the registers above and their id-code. 6 system operating modes xx-xe88lc01/03/05, data book page 56 20001101 preliminary in f ormation after any system reset the regevnpriority value is hff indicating no event request has been issued subsequent to the reset. the second, regevnevn, indicates the priority levels of the current events. the two levels of events map directly to those supported by the coolrisc (ev0 & ev1). for more information, see the documentation about the coolrisc816 core. regevnpriority event priority (on cpu) highest priority event set hff none no event h07 ev0 (high) evncnta h06 ev0 (high) evncntc h05 ev0 (high) evnpre1 h04 ev0 (high) evnpa[1] h03 ev1 (low) evncntb h02 ev1 (low) evncntd h01 ev1 (low) evnpre2 h00 ev1 (low) evnpa[0] table 6.18: all events and their priorities register name address (hex) regevn h003c regevnen h003d regevnpriority h003e regevnevn h003f table 6.19: event registers bit name reset rw description 7 evncnta 0 resetsystem rc1 event from counter a 6 evncntc 0 resetsystem rc1 event from counter c 5 evnpre1 0 resetsystem rc1 event from prescaler (128 hz) 4 evnpa[1] 0 resetsystem rc1 event from pad pa[1] 3 evncntb 0 resetsystem rc1 event from counter b 2 evncntd 0 resetsystem rc1 event from counter d 1 evnpre2 0 resetsystem rc1 event from prescaler (1 hz) 0 evnpa[0] 0 resetsystem rc1 event from pad pa[0] table 6.20: regevn bit name reset rw description 7 evnencnta 0 resetsystem rw enable event from countera 6 evnencntc 0 resetsystem rw enable event from counterc 5 irqrenpre1 0 resetsystem rw enable event from prescaler (128 hz) 4 evnenpa[1] 0 resetsystem rw enable event from pad pa[1] 3 evnencntb 0 resetsystem rw enable event from counterb 2 evnencntd 0 resetsystem rw enable event from counterd 1 irqrenpre1 0 resetsystem rw enable event from prescaler (1 hz) 0 evnenpa[0] 0 resetsystem rw enable event from pad pa[0] table 6.21: regevnen bit name reset rw description 7-0 evnpriority hff resetsystem r code of highest priority set interrupt table 6.22: regevnpriority xx-xe88lc01/03/05, data book 6 system operating modes 20001101 page 57 preliminary information 6.5 miscellaneous 6.5.1 port configuration reset port configuration (pins in input or output mode) is controlled by registers described in the ports chapters. these registers are initialized by signal resetpconf that the user can configure as active or inactive during system reset with bit enrespconf in register regsysctrl . the user can also choose if these registers are initialized for each reset or only on power-on reset. 6.5.2 prescaler interrupt synchronization prescaler generates two interrupts at frequencies 128 hz and 1 hz. interrupt signal is generated on negative slope so that 1hz interrupt is generated one second after prescaler initialization, and then subsequently each second. bit name reset rw description 7-2 -- 000000 r unused 1 evnhig 0 resetsystem r one (or more) high priority event is set 0 evnlow 0 resetsystem r one (or more) low priority event is set table 6.23: regevnevn bit name reset rw description 7-0 evntest 00000000 resetsystem wt for test only table 6.24: regevntest bitenrespconf port config reset 1 reset with any reset source 0 reset with resetcold only (power-on reset) table 6.25: port config reset figure 6.8: port configuration reset resetpconf resetcold ck_regsysmisc datain[6] reset synchronizer enrespconf resetsys porta figure 6.9: prescaler interrupt synchronization irq(pre0) resetdivxtal ck128 prescaler irq(pre1) resetdivxtal ck1 prescaler 6 system operating modes xx-xe88lc01/03/05, data book page 58 20001101 preliminary in f ormation 6.6 digital debouncer a digital debouncer can be used to filter input pins of porta. period of the debouncer is set by bit debfast in register regsysmisc . 6.6.1 description at power-on, signal resetcold is activated by power-on reset block. debfast is initialized at 0 (ckdeb = 4 ms) digital filter is initialized at 0 (not active). debouncer period can be set to 125 us or 4 ms with bit debfast . input signal must be stable during the complete debouncer period to be transmitted. note: debouncer clock is taken from the prescaler, and so may vary with actual rc frequency. note: debouncer delay varies with the respective phases of the input signal and the debouncer clock. 6.7 system peripheral addresses debfast debouncer period 1 125 us 0 3.9 ms table 6.26: debouncer frequency register addresses regsysctrl h0010 regsysreset h0011 regsysclock h0012 regsysmisc h0013 regsyswd h0014 regsyspre0 h0015 regsyspre1 h0016 reserved h0017 reserved h0018 reserved h0019 reserved h001a regsysrctrim1 h001b regsysrctrim2 h001c regsysvireg h001d reserved h001e regsyswarm h001f table 6.27: system address ranges xx-xe88lc01/03/05, data book 7 oscillators 20001101 page 59 preliminary information 7 oscillators there are two oscillators: one fast programmable rc oscillator, and a precise crystal oscillator. registers for con- trolling the oscillators are described in the system chapter. 7.1 rc oscillator 7.1.1 rc oscillator principle the rc oscillator is always turned on at power-on reset and can be turned off after the optional xtal oscillator has been started. the rc oscillator has two frequency ranges: sub-mhz (100khz to 1mhz) and above-mhz (1mhz to 10mhz). inside a range, the frequency can be tuned by software for coarse and fine adjustment. no external components are required as both the resistor and the capacitor are on chip. the rc oscillator can be in 3 modes. in mode 1(rc on), the rc oscillator and its bias are on. in mode 2 (rc ready), the rc oscillator is off and the bias is on. in mode 3 (rc off), the rc oscillator and the bias are off. rc ready mode is a compromise between power consumption and start-up time. figure 7.1: rc programming principle range coarse fine 80 khz 800 khz 1 16 0.6 1.5 programmable oscillator figure 7.2: rc frequencies programming example for low range (typical values) 7 oscillators xx-xe88lc01/03/05, data book page 60 20001101 preliminary in f ormation 7.1.2 rc divider cold start during rc oscillator start-up, the coldstart structure masks the first system clock cycles. two bits enablerc and coldrc in register regsysclock control this coldstart structure. at power-on, resetcold signal initialize enablerc and coldrc to 1 (selects rc oscillator). rc oscillator starts and some cycles later bit coldrc is reset and the clock is made available to the system after one additionnal clock cycle delay. rc oscillator can be stopped by the user by resetting bit enablerc . in this case, bit coldrc goes immediately to 1. by setting bit enablerc , one restarts the rc oscillator. eight cycles later, bit coldrc is reset and clock is made available to the system after one additionnal clock cycle delay. when user sets sleep mode, signal sleep is set together with bits enablerc and coldrc . signal rcpower is masked to maintain oscillator stopped. when coming out of sleep mode, usual start-up happens. rc oscillator starts on port a event if resonpa0 is set in regsysmisc . note: prescaler is initialized by signal bitsleep . note: rc oscillator bias is set by bit bitbiasrc in regsysclock . symbol description min typ max unit comments f st frequency at start-up 50 80 110 khz range range selection 1 10 multiplies f st mult[3:0] coarse tuning range 1 16 4 bits, multiplies f st * range tune[5:0] fine tuning range 0.65 1.5 6 bits, multiplies f st * range * mult fine tuning step 1.4 2 % t st start-up time 30 50 m s bias current is off (rc off) o st overshoot at start-up 50 % bias current is off (rc off) t wu wakeup time 3 5 m s bias current is on (rc ready) o wu overshoot at wakeup 50 % bias current is on (rc ready) jit jitter rms 2 o / oo table 7.1: rc specifications bit name reset rw description 7-6 -- 00 r unused 5 enrcrext 0 resetcold rw enable external resistor for trimming 4 rcfreqrange 0 resetcold rw low- / high-frequency rc (0=low) 3 rcfreqcoarse[3] 0 resetcold rw rc frequency coarse trimming bit 3 2 rcfreqcoarse[2] 0 resetcold rw rc frequency coarse trimming bit 2 1 rcfreqcoarse[1] 0 resetcold rw rc frequency coarse trimming bit 1 0 rcfreqcoarse[0] 0 resetcold rw rc frequency coarse trimming bit 0 table 7.2: regsysrctrim1 bit name reset rw description 7-6 -- 00 r unused 5 rcfreqfine[5] 1 resetcold rw rc frequency fine trimming bit 5 4 rcfreqfine[4] 0 resetcold rw rc frequency fine trimming bit 4 3 rcfreqfine[3] 0 resetcold rw rc frequency fine trimming bit 3 2 rcfreqfine[2] 0 resetcold rw rc frequency fine trimming bit 2 1 rcfreqfine[1] 0 resetcold rw rc frequency fine trimming bit 1 0 rcfreqfine[0] 0 resetcold rw rc frequency fine trimming bit 0 table 7.3: regsysrctrim2 xx-xe88lc01/03/05, data book 7 oscillators 20001101 page 61 preliminary information 7.2 xtal oscillator 7.2.1 general description the xtal oscillator operates with an external crystal of 32768 hz. note: board layout recommendations for safer crystal oscillation and lower current consumption: ? keep lines xtal_in and xtal_out short and insert a vss line between them. ? connect package of the crystal to vss. ? no noisy or digital lines near xtal_in and xtal_out. ? insert guards at vss where needed. 7.2.2 typical external component the crystal oscillator needs a 32768 hz crystal with specifications as in table 7.5 (normal watch crystal). attention has to be made when designing the board, especially to the parameters given in table 7.6. 7.2.3 xtal divider cold start during xtal oscillator start-up, a cold start structure masks the first 32768 clock cycles. the two bits enablextal and bitcoldxtal in register regsysclock control this structure. 7.2.4 description at power-on, signal resetcold resets enablextal and sets coldxtal (xtal oscillator is not selected at start-up). symbol description min typ max unit comments f_clk32k nominal frequency 32768 hz st_x32k oscillator start-up time 1 2 s duty_clk32k duty cycle on the digital output 30 50 70 % fstab_1 relative frequency deviation from nominal, for a crystal with cl=8.2 pf and temperature between -40 and +85c -100 +300 ppm not included: crystal frequency tolerance and aging crystal frequency - temperature dependence table 7.4: xtal oscillator specifications. symbol description min typ max unit comments fs resonance frequency 32768 hz cl cl for nominal frequency 8.2 pf rm motional resistance 40 100 k w cm motional capacitance 1.8 2.5 3.2 ff c0 shunt capacitance 0.7 1.1 2.0 pf q quality factor 40k 80k 400k - table 7.5: external crystal specifications. 32 khz xtal outside these specifications will must probably delivers correct frequency, but some precision specifications will be released. symbol description min typ max unit rh_xin external board parasitic resistance xtal_in - vss 10 m w rh_xout external board parasitic resistance xtal_out - vss 10 m w rh_xin_xout external board parasitic resistance xtal_in - xtal_out 50 m w cp_xin external board parasitic capacitance on xtal_in - vss 0.5 3.0 pf cp_xout external board parasitic capacitance on xtal_out - vss 0.5 3.0 pf cp_xin-xout external board parasitic capacitance xtal_in - xtal_out 0.2 1.0 pf table 7.6: board design specifications 7 oscillators xx-xe88lc01/03/05, data book page 62 20001101 preliminary in f ormation xtal oscillator can be started by the user by setting enablextal . bit enextclk should be reset first to disable external clock detection. if an external clock is already detected, xtal oscillator can not be started anymore (blocked by ext- clk ). when xtal oscillator starts, bit coldxtal is reset after 32768 cycles and clock is made available to the system. xtal oscillator can be stopped by user by resetting bit enablextal . in this case, bit coldxtal is immediately set. when the user chooses sleep mode, signal sleep going to 1 resets enablextal and sets coldxtal . when going out of sleep mode the oscillator is stopped until being started by the user. note: prescaler is initialised by signal sleep . 7.3 external clock an external clock can be provided by the user instead of the xtal oscillator. the clock is input through the pin oscin. if the external clock is present, it is detected after 4 cycles (extclk set) and the xtal oscillator is disabled (not possible to set enablextal ). note: after power-up, the external clock detection is disabled ( enextclk is off). if the user wants to use the ex- ternal oscillator, the bit enextclk has to be set to 1. note: extclk can be reset by power-on reset only. 7.4 oscillators control both rc and xtal oscillators can be controlled by changing the states of selected bits with regsysclock . after pow- er-on reset, only the rc oscillator is running. 7.4.1 cpu clock as there are three different clock sources available for the cpu clock, it is possible to select one of them. the rc clock is always selected after power-up or after sleep mode. the cpu clock selection is done with the bit cpusel in regsysclock (0=rc clock, 1 = xtal clock or external clock). note: if a clock is selected but its oscillator is in cold start phase, the cpu clock is stopped during that time. note: switching from rc clock to xtal clock and stopping the rc must be performed using 2 move instructions to regsysclock . first select the xtal clock and then stop the rc. when switching form xtal to rc clock, first select the rc clock and then stop the xtal. note: if only one clock is active (rc or xtal), that clock is selected per default. at power-on, or when going to sleep mode, signal resetsleep (resetcold or bitsleep) resets cpusel , rc oscillator is chosen. cpusel coldrc coldxtal bitextclk sel ckcpu x11000 0 0 x x 0 ckrc 1 0 1 0 0 ckrc 0 1 0 x 1 ckxtal 0 1 1 1 1 extclk 1 x 0 x 1 ckxtal 1 x 1 1 1 extclk table 7.7: cpu clock selection xx-xe88lc01/03/05, data book 7 oscillators 20001101 page 63 preliminary information note: selection of clock is made without glitches thanks to a specific block (see figure 7.3). 7.4.2 oscillator register ? biasrc enables the rc oscillator bias current for a fast start-up ? coldxtal this bit is set during the cold start of the xtal oscillator. the delay is 32768 clock cycles ? coldrc this bit is set during the cold start of the rc oscillator. the delay is 8 clock cycles ? enablextal enables the xtal oscillator. this bit is set after power-on. ? enablerc enables the rc oscillator note: if the extclk bit is one, then the enextclk bit must not be set to 0. 7.5 prescaler the prescaler is a divider chain providing frequencies down to 1hz based on the rc oscillator or based on the xtal oscillator. two registers regsyspre0 and regsyspre1 control the prescaler. the prescaler is made of one asynchronous 8 stage divider and one asynchronous 15 stage divider, all chained, and of one initialization structure. 7.5.1 features ? basic 15 stage divider in case of 32768hz -> 1hz ? low 15 stages can be reset with a reset prescaler command ? all 15 divided clocks are outputs which can be used in other blocks like timer/counter, debouncer, eol logic, oscillation detector, wd, used outputs from 15 stage dividers are 32khz, 1024hz, 256hz, 128hz, 1hz ? rc oscillator itself has a divider by 32 to accept 1mhz clock and output for other peripherals 1mhz, 250 khz and 31 khz clocks ? prescaler as divider chain and clock selector can be tested separately. (this means independent of other blocks) ? with test register we can read state of the divider chain after each 4 dividers, (after 2 dividers for hi-frequency rc clock) ? prescaler has a reset input to reset the whole divider chain. this can be the sum of por and reset pad bit name reset rw description 7 cpusel 0 resetsleep r w ckcpu selection (0=rc) 6 extclk 0 resetcold r external clock detected 5 enextclk 0 resetcold r w enable oscin to be driven from ext. 4 biasrc 1 resetcold r w enable rc bias when enablerc = 0 3 coldxtal 1 resetsleep r xtal in starting phase for 32768 cycles 2 coldrc 1 resetsleep r rc in starting phase for 8 cycles 1 enablextal 0 resetsleep r w enable xtal oscillator (cannot be set if enextclk=1 or extclk=1) 0 enablerc 1 resetsleep r w enable rc oscillator table 7.8: regsysclock, address h0012 figure 7.3: cpu clock selection crrc sel ckxtal ckcpu 7 oscillators xx-xe88lc01/03/05, data book page 64 20001101 preliminary in f ormation 7.5.2 description the 8 stages divider is directly connected to the rc oscillator. the 15 stages dividers is clocked by the xtal oscillator when it is on, or by a frequency near to 32 khz taken from the first divider based on the rc oscillator trimming. see examples below (figure 7.4, table 7.9). additionnal circuitry, not shown on the figure, prevents unwanted transitions on ck32k when switching the rc oscillator frequency. signal resetcold initializes all dividers at power-on. the 8-bits divider and the remaining 5-bits dividers use different initialization signals. the 3 low frequency dividers can be reset simultaneously by writing bxxxxxxx1 in register regsyspre0 . these dividers are also initialized at freq name clocks rc@4mhz, xtal off rc@2.5mhz, xtal off rc@1mhz, xtal off rc@1mhz, xtal on rc off, xtal on coarse (3:0) 0100b n/a fine (5:0) 100001b n/a ckrc 20 4000000 2457600 1040000 1040000 off ck500k 19 2000000 1228800 520000 520000 off ck250k 18 1000000 614400 260000 260000 off ck125k 17 500000 307200 130000 130000 off ck62k 16 250000 153600 65000 65000 off ckxtal off off off 32768 32768 ck64k to ck32k divider 842n/an/a ck32k 15 31250 38400 32500 32768 32768 ck16k 14 15625 19200 16250 16384 16384 ck8k 13 7813 9600 8125 8192 8192 ck4k 12 3906 4800 4062 4096 4096 ck2k 11 1953 2400 2031 2048 2048 ck1k 10 977 1200 1016 1024 1024 ck512 9 488 600 508 512 512 ck256 8 244 300 254 256 256 ck128 7 122 150 127 128 128 ck64 6 61 75 63.5 64 64 ck32 5 31 37.5 31.7 32 32 ck16 4 15.3 18.8 15.9 16 16 ck837.639.387.9388 ck423.814.693.9744 ck211.912.341.9822 ck1 0 0.95 1.17 0.992 1 1 watchdog -- 4.19 seconds 3.41 seconds 4.03 seconds 4 seconds 4 seconds table 7.9: frequency examples, typical values for rc setting, range is set to 1 divider 8 stages figure 7.4: prescaler principle sleep coldxtal clearpre resetdivrc resetdivxtal enablextal resetcold 1 0 divider 5 stages divider 5 stages divider 5 stages ckrc ckxtal ck500k ck250k ck125k ck62k ck32k ck16k ck8k ck4k ck2k ck1k ck512 ck256 ck128 ck64 ck32 ck16 ck8 ck4 ck2 ck1 wd rctrimm + glue prescaler synchronise and control rc oscillator xtal oscillator xx-xe88lc01/03/05, data book 7 oscillators 20001101 page 65 preliminary information xtal oscillator start (writing bxxxxxxx1x in register regsysclock ). initialization signal is synchronized to the low frequency clock in order to ensure correct divider initialization. note: dividers are initialised in mode sleep. note: low frequency part of prescaler is not initialised by the reset synchronizer (clearpre) when xtal oscillator is in coldstart so that the coldstart delay is not disturbed. note: low frequency part of prescaler is always set after the high frequency part (connected to rc) when external clock is selected. note: unless ck32k is taken from the xtal oscillator, its frequency can significantly dif- fer from its nominal value. 7.5.3 registers the regsyspre0 controls some of the prescaler functions. the bits within the registers define the following: ? cpuclk internal cpu clock in internal test mode only ? respre when 1 is written at this address only the low 15 stage xtal divider is reset to 0. this reset takes one xtal clock period enxtal rc trimming rc frequency division factor low prescaler input freq range coarse regsysrc- trim2 = 00 regsysrc- trim2 = 20 regsysrc- trim2 = 3f regsysrc- trim2 = 00 regsysrc- trim2 = 20 regsysrc- trim2 = 3f 1xxxxxxxxx 32768 0 0 0000 56560 80000 112800 2 28280 40000 56400 0 0 0001 113120 160000 225600 4 28280 40000 56400 0 0 0010 169680 240000 338400 8 21210 30000 42300 0 0 0011 226240 320000 451200 8 28280 40000 56400 0 0 0100 282800 400000 564000 16 17675 25000 35250 0 0 0101 339360 480000 676800 16 21210 30000 42300 0 0 0110 395920 560000 789600 16 24745 35000 49350 0 0 0111 452480 640000 902400 16 28280 40000 56400 0 0 1000 509040 720000 1015200 16 31815 45000 63450 0 0 1001 565600 800000 1128000 32 17675 25000 35250 0 0 1010 622160 880000 1240800 32 19443 27500 38775 0 0 1011 678720 960000 1353600 32 21210 30000 42300 0 0 1100 735280 1040000 1466400 32 22978 32500 45825 0 0 1101 791840 1120000 1579200 32 24745 35000 49350 0 0 1110 848400 1200000 1692000 32 26513 37500 52875 0 0 1111 904960 1280000 1804800 32 28280 40000 56400 0 1 0000 565600 800000 1128000 32 17675 25000 35250 0 1 0001 1131200 1600000 2256000 64 17675 25000 35250 0 1 0010 1696800 2400000 3384000 64 26513 37500 52875 0 1 0011 2262400 3200000 4512000 128 17675 25000 35250 0 1 0100 2828000 4000000 5640000 128 22094 31250 44063 0 1 0101 3393600 4800000 6768000 128 26513 37500 52875 0 1 0110 3959200 5600000 7896000 128 30931 43750 61688 table 7.10: automatic input frequency selection, typical values. values in italic are not allowed and may result in unpredictable cpu behaviour. bit name reset rw description 7-2 -- 000000 r unused 1 cpuclk 0 r cpuclk in test mode 0 respre 0 resetcold w reset the xtal prescaler when written to 1 table 7.11: regsyspre0 7 oscillators xx-xe88lc01/03/05, data book page 66 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 8 parallel io ports 20001101 page 67 preliminary information 8 parallel io ports 8.1 port a 8.1.1 features ? input port, 8 bits wide ? regpain read the input status after the debouncer option ? each bit can be set individually for debounced or direct input ? each bit can be set individually for pullup or not ? each bit is an interrupt request source and can be set on rising or falling edge ? a system reset can be generated on a port configuration, each bit as direct input, inverted input, zero or one ? pa[0] and pa[1] can generate two events for the cpu, individually maskable ? pa[0] to pa[3] can be used as clock inputs for the counters 8.1.2 overview port a is a general purpose 8 bit wide input port, with interrupt capability. it can be debounced or not. internal pull-up resistors can be connected to its inputs. it can be used to connect external clock sources for the internal counters (also event counter capability). rising or falling edge for interrupt generation can be selected, pa[0] and pa[1] can generate events for the cpu. 8.1.3 port a configuration the porta input status can be read from regpain . each bit of porta can be set individually to be a debounced or a direct input using register regpadebounce (input is debounced if 1 is written in). following reset, this register is 0. figure 8.1: port a regpaedge internal bus 8 regpapullup 8 regpatest 4 regpain 8 0 1 p_in[7:0] port a regpadebounce 8 regpares1 8 regpares0 8 0 1 10 11 01 00 interrupts 0 1 debounce 8x 8x resetpa 8 parallel io ports xx-xe88lc01/03/05, data book page 68 20001101 preliminary in f ormation note: depending on the status of an enrespconf bit in regsysctrl , regpadebounce can be reset by any of the possible system resets or only with power-on reset (por). each porta input is an interrupt request source and can be set on rising or falling edge with a regpaedge. following reset, the rising edge is selected for interrupt generation by default. note: care must be taken when modifying regpaedge because this register performs a selection, the dynamic result of which may be interpreted incorrectly as a transition. it is therefore better to remove the correspond- ing porta irqmask in regirqenmid and regirqenlow when changing regpaedge . interrupt flag is set only when its corresponding irqmask bit is set to 1. each bit can be set individually for pullup or not using register regpapullup . input is pulled-up when its corre- sponding bit in this register is set to 1. default status after reset is 0 what means no pull_up. note: depending on the status of an enrespconf bit in regsysctrl , regpaedge can be reset by any of the possible system resets or only with poweronreset (por). see table 8.1. porta can be used to generate a system reset by placing a predetermined word on porta externally. the precise code that will cause a system reset can be set with the aid of table 8.1. two registers regpares0 and regpares1 (bit as direct input, inverted input, zero or one) can select one of four possibilities shown in this table. the logical and combination of all 8 input lines with their selection (shown in the column pares[x]) can give a re- setporta as one of system reset sources. resetporta = pares[7] and pares[6] and pares[5] and ... and pares[0] note: a reset via port a can be inhibited by placing a 0 on both pares1[x] and pares0[x] (for a particular x). pa[0] to pa[3] can be used as clock input for the counters, a, b, c & d respectively. in this case counters can be used as event counters of pa[0]..pa[3]. counter inputs can be debounced or not, depending on regpadebounce . additionally, the counting edge (falling or rising) can be selected using regpaedge. pares1[x] pares0[x] pares[x] 11 1 10not pa[x] 0 1 pa[x] 00 0 table 8.1: reset selection for each pin porta input external clock for counter pa[0] countera pa[1] counterb pa[2] counterc pa[3] counterd table 8.2: clock inputs for counters ckdeb figure 8.2: digital debouncer debounced input 11112 12 xx-xe88lc01/03/05, data book 8 parallel io ports 20001101 page 69 preliminary information 8.1.4 porta registers register name address (hex) regpain h0020 regpadebounce h0021 regpaedge h0022 regpapullup h0023 regpares0 h0024 regpares1 h0025 regpatest h0027 table 8.3: port a registers bit name reset rw description 7-0 pain[7-0] xxxxxxxx r pad pa[7-0] input status table 8.4: register regpain bit name reset rw description 7-0 padeb[7] 00000000 resetpconf rw debounce for pa[7-0] (1=debounce) table 8.5: register regpadebounce bit name reset rw description 7-0 paedge[7-0] 00000000 resetsystem rw edge selection for irqpa[7-0] (0=rise) table 8.6: register regpaedge bit name reset rw description 7-0 papullup[7-0] 00000000 resetpconf rw pullup for pad pa[7-0] (1=active) table 8.7: register regpapullup bit name reset rw description 7-0 pares0[7-0] 00000000 resetsynch rw reset selection bit 0 for pad pa[7-0] table 8.8: regpares0 bit name reset rw description 7-0 pares1[7-0] 0 resetsynch rw reset selection bit 1 for pad pa[7-0] table 8.9: regpares1 bit name reset rw description 7-4 -- 0000 r unused 3 patest[3] 0 resetsystem r resetporta 2 patest[2] 0 resetsystem rw patest = irqbus in test mode 1 patest[1] 0 resetsystem rw 8 bits of irqbus in test mode 0 patest[0] 0 resetsystem rw irqbus = 8 x patest1 in test mode table 8.10: regpatest 8 parallel io ports xx-xe88lc01/03/05, data book page 70 20001101 preliminary in f ormation 8.2 port b 8.2.1 features ? input / output / analog port, 8 bits wide ? each bit can be set individually for input or output ? each bit can be set individually for open-drain or push-pull ? each bit can be set individually for pullup or not ? four pairs of pads which can be connected individually to four internal analog lines (4 line analog bus) ? pullup is not active when corresponding pad is set to zero ? two pwm can be output on pads pb[0] and pb[1] ? two internal freq (xtal and cpu) can be output on pb[2] and pb[3] ? the synchronous serial interface uses pads pb[5], pb[4] and pb[3] for sin, scl and sou ? pb[0] is used in test mode for cpu test output ? the uart interface uses pads pb[6] and pb[7] for tx and rx 8.2.2 overview portb is a multi-purpose 8 bit input/output port. in addition to digital behaviour, all pins can be used for analog sig- nals. each port terminal can be individually selected as digital input or output or in pairs as analog for sharing one of four possible analog lines. 8.2.3 port b digital capabilities when used as logic outputs, each can be individually set as an n-channel open-drain or a push-pull (conventional) output. each pin can be individually set to use internal pull-ups. figure 8.3: port b regpbout internal bus 8 regpbdir 8 regpbin 8 p_out[7:0] p_enable[7:0] p_in[7:0] port b regpbopen 8 regpbpullup 8 regpbana 4 portb internal vdd analog bus 1 0 4 xx-xe88lc01/03/05, data book 8 parallel io ports 20001101 page 71 preliminary information data is stored in regpbout prior to output at portb.this occurs provided that pbdir[x] has been set high (1), ac- cordingly. its default following reset is low (0). the status of portb is available in regpbin (read only). reading is always direct - there is no debounce function associated with portb. in case of possible noise on input signals, a software debouncer with pooling must be real- ized. the direction of each bit within portb (input or output) can be individually set using the regpbdir register. if pb- dir[x] = 1, the corresponding portb pin becomes an output. following reset portb is in input mode ( pbdir[x] are reset to 0). when a pin is in output mode (its pbdir[x] is set to 1), the output can be conventional cmos (push-pull) or n-chan- nel open-drain. driving the output only low. by default, after por the pbopen[x] in regpbopen is cleared to 0 (push-pull). if pbopen[x] in regpbopen is set to 1 then the internal p transistor in the output buffer is electrically removed and the output can only be driven low. when the output should be high the pin becomes high impedance. the internal pull-up or external pull-up resistor can be used to drive to pin high if required. note: because the p transistor actually exists (this not a real open-drain output) the pull-up range is limited to avoid forward bias the p transistor / diode (vdd + 0.2v). each bit can be set individually for pullup or not using register regpbpullup . input is pulled-up when its corre- sponding bit in this register is set to 1. default status after reset is 0 which means no pull_up. to conserve power, pull-ups are only enabled when the associated pin is either a digital input or on an n-channel open-drain output. when the counters are used to implement a pwm function, the pb[0] and pb[1] terminals are declared as outputs and override other values written in regpbout . pbdir(0) and pbdir(1) must be set to 1. if outputckxtal is set in regsysmisc the xtal frequency is output on pb[3]. this overrides the value contained in regpbout . similarly, if outputckcpu is set in regsysmisc , the cpu frequency is output on pb[2]. this overrides the value contained in regpbout . pbdir(2) and pbdir(3) must be set to 1. pins pb[5] and pb[4] can be used for serial data (sin) and serial clock (scl) when the enableusrt bit is set in usrtctrl . when enableusrt is set the pb[5] and pb[4] bidirectional become open-drain ( regpbopen is not changed). if there is no external pull-up resistor on these pins, this must be set to be pull-ups in regpbpullup . when used as output and in synchronous serial mode, outputs take the value of usrtsin and usrtscl bits from their respective registers regusrtsin and regusrtscl . when entx in reguartctrl is set, pb[6] is output signal tx. when enrx in reguartctrl is set, pb[7] is input signal rx. port b name utilisation (priority) high medium low pb[7] analog usart rx i/o pb[6] usart tx i/o pb[5] analog synchronous serial i/o pb[4] i/o pb[3] analog clock 32khz i/o pb[2] clock cpu i/o pb[1] analog pwm1 counter c (c+d) i/o pb[0] pwm0 counter a (a+b) i/o table 8.11: different portb functions 8 parallel io ports xx-xe88lc01/03/05, data book page 72 20001101 preliminary in f ormation 8.2.4 port b analog capability portb terminals can be attached to 4 line analog bus in pairs by setting the pbana[x] bits in regpbana register. with other registers we can program sharing of this 4 analog lines between different pads of portb. this can be used to implement simple lcd driver or a/d converters. analog switching is available only when the circuit is powered with sufficient voltage. when pbana[x] is set to 1, changing one pair of the portb terminals from digital i/o mode to analog, the corre- sponding regpbpullup, regpbout and regpbdir change their functions. example: when pbana[0] is set to 1 then the interpretation of two lsbs (bit0 and bit1) in regpbout and regpbdir change. pb[0] and pb[1] become analog pins. the other portb pins (pb[7]..pb[2]) stay digital. the selection is performed with regpbout and regpbdir . the analog line to which the appropriate signal is con- nected is determined by the codes placed on regpbout and regpbdir according to the following table. in the context of the example where pbana[0] is set to 1: to connect pb[0] to analog line 3 and pb[1] to analog line 2 would require that f( regpbdir [1], regpbdir [0]) = (1,1) and that f( regpbout [1], regpbout [0]) = (1,0). regpbtest is used for internal test purposes.it can not be influenced by user outside test mode. in normal mode it is always read as 0. note: depending on the status of an enrespconf bit in regsysctrl , some registers can be reset by any of the possible system resets or only with poweronreset (por). selection bits from regpbdir or regpbou pb[x] selection on 0 0 analog line 0 0 1 analog line 1 1 0 analog line 2 1 1 analog line 3 table 8.12: selection for analog lines with regpbdir (pads b0, b2, b4 and b6) or regpbout (pads b1, b3, b5 and b7) register name address (hex) regpbout h0028 regpbin h0029 regpbdir h002a regpbopen h002b regpbpullup h002c regpbana h002d reserved h002e h002f table 8.13: port b registers bit name reset rw description 7-0 pbin[7-0] x r pad pb[7-0] input status table 8.14: regpbin bit name reset rw description 7-0 pbopen[7-0] 0 resetpconf rw pad pb[7-0] opendrain (1=opendrain) table 8.15: regpbopen xx-xe88lc01/03/05, data book 8 parallel io ports 20001101 page 73 preliminary information 8.3 port c 8.3.1 features ? input / output port, 8 bits wide ? each bit can be set individually for input or output ? push-pull output only 8.3.2 overview portc is a general purpose 8 bit input/output port. data is stored in regpcout prior to output at portc. this occurs provided that pcdir[x] has been set high (1), ac- cordingly. its default following reset is low (0). the status of portc is available in regpcin (read only). reading is always direct - there is no digital debounce func- tion associated with portc. in case of possible noise of input signals, a software debouncer with pooling must be realized. bit name reset rw description 7-4 -- 0000 r used 3 pbana[3] 0 resetpconf rw set pb[7] and pb[6] in analog mode 2 pbana[2] 0 resetpconf rw set pb[5] and pb[4] in analog mode 1 pbana[1] 0 resetpconf rw set pb[3] and pb[2] in analog mode 0 pbana[0] 0 resetpconf rw set pb[1] and pb[0] in analog mode table 8.16: regpbana bit name reset rw description in digital mode descriptionin analog mode 7-0 pbpullup[7-0] 0 resetpconf rw pullup for pad pb[7-0] (1=active) connect pad pb[7-0] on selected ana bus table 8.17: regpbpullup bit name reset rw description in digital mode description in analog mode 7 pbout[7] 0 resetpconf rw pad pb[7] output value analog bus selection bit 1 for pad pb[7] 6 pbout[6] 0 resetpconf rw pad pb[6] output value analog bus selection bit 0 for pad pb[7] 5 pbout[5] 0 resetpconf rw pad pb[5] output value analog bus selection bit 1 for pad pb[5] 4 pbout[4] 0 resetpconf rw pad pb[4] output value analog bus selection bit 0 for pad pb[5] 3 pbout[3] 0 resetpconf rw pad pb[3] output value analog bus selection bit 1 for pad pb[3] 2 pbout[2] 0 resetpconf rw pad pb[2] output value analog bus selection bit 0 for pad pb[3] 1 pbout[1] 0 resetpconf rw pad pb[1] output value analog bus selection bit 1 for pad pb[1] 0 pbout[0] 0 resetpconf rw pad pb[0] output value analog bus selection bit 0 for pad pb[1] table 8.18: regpbout bit name reset rw description in digital mode description in analog mode 7 pbdir[7] 0 resetpconf rw pad pb[7] direction (0=input) analog bus selection bit 1 for pad pb[6] 6 pbdir[6] 0 resetpconf rw pad pb[6] direction (0=input) analog bus selection bit 0 for pad pb[6] 5 pbdir[5] 0 resetpconf rw pad pb[5] direction (0=input) analog bus selection bit 1 for pad pb[4] 4 pbdir[4] 0 resetpconf rw pad pb[4] direction (0=input) analog bus selection bit 0 for pad pb[4] 3 pbdir[3] 0 resetpconf rw pad pb[3] direction (0=input) analog bus selection bit 1 for pad pb[2] 2 pbdir[2] 0 resetpconf rw pad pb[2] direction (0=input) analog bus selection bit 0 for pad pb[2] 1 pbdir[1] 0 resetpconf rw pad pb[1] direction (0=input) analog bus selection bit 1 for pad pb[0] 0 pbdir[0] 0 resetpconf rw pad pb[0] direction (0=input) analog bus selection bit 0 for pad pb[0] table 8.19: regpbdir 8 parallel io ports xx-xe88lc01/03/05, data book page 74 20001101 preliminary in f ormation the direction of each bit within portc (input or output) can be individually set using the regpcdir register. if pcdir[x] = 1, the corresponding portc pin becomes an output. following reset portc is in input mode ( pcdir[x] are reset to 0). note: depending on the status of an enrespconf bit in regsysctrl , this register can be reset by any of the pos- sible system resets or only with poweronreset (por). see table table 8.1. register name address (hex) regpcout h0030 regpcin h0031 regpcdir h0032 reserved h0033 table 8.20: port c registers bit name reset rw description 7 pcout[7] 0 resetpconf r w pad pc[7] output value 6 pcout[6] 0 resetpconf r w pad pc[6] output value 5 pcout[5] 0 resetpconf r w pad pc[5] output value 4 pcout[4] 0 resetpconf r w pad pc[4] output value 3 pcout[3] 0 resetpconf r w pad pc[3] output value 2 pcout[2] 0 resetpconf r w pad pc[2] output value 1 pcout[1] 0 resetpconf r w pad pc[1] output value 0 pcout[0] 0 resetpconf r w pad pc[0] output value table 8.21: regpcout bit name reset rw description 7 pcin[7] x r pad pc[7] input status 6 pcin[6] x r pad pc[6] input status 5 pcin[5] x r pad pc[5] input status 4 pcin[4] x r pad pc[4] input status 3 pcin[3] x r pad pc[3] input status 2 pcin[2] x r pad pc[2] input status 1 pcin[1] x r pad pc[1] input status table 8.22: regpcin figure 8.4: port c regpcout internal bus 8 regpcdir 8 regpcin 8 p_out[7:0] p_enable[7:0] p_in[7:0] port c xx-xe88lc01/03/05, data book 8 parallel io ports 20001101 page 75 preliminary information 8.3.3 port d is identical to port c. 0 pcin[0] x r pad pc[0] input status bit name reset rw description 7 pcdir[7] 0 resetpconf r w pad pc[7] direction (0=input) 6 pcdir[6] 0 resetpconf r w pad pc[6] direction (0=input) 5 pcdir[5] 0 resetpconf r w pad pc[5] direction (0=input) 4 pcdir[4] 0 resetpconf r w pad pc[4] direction (0=input) 3 pcdir[3] 0 resetpconf r w pad pc[3] direction (0=input) 2 pcdir[2] 0 resetpconf r w pad pc[2] direction (0=input) 1 pcdir[1] 0 resetpconf r w pad pc[1] direction (0=input) 0 pcdir[0] 0 resetpconf r w pad pc[0] direction (0=input) table 8.23: regpcdir bit name reset rw description table 8.22: regpcin 8 parallel io ports xx-xe88lc01/03/05, data book page 76 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 9 universal asynchronous receiver/transmitter (uart) 20001101 page 77 preliminary information 9 universal asynchronous receiver/transmitter (uart) 9.1 features ? full duplex operation with buffered receiver and transmitter. ? internal baudrate generator with 8 programmable baudrate (300 - 38400). ? 7 or 8 bits word length. ? even, odd, or no-parity bit generation and detection ? 1 stop bit ? error receive detection : start, parity, frame and overrun ? receiver echo mode ? 2 interrupts (receive full and transmit empty) ? enable receive and/or transmit ? invert pad rx and/or tx 9.2 overview the uart hardware is tied to pb[7] which is used as rx - receive and pb[6] as tx - transmit. 9.3 uart prescaler in order to have correct baudrates, the uart interface has to fed with a stable and trimmed clock source. it can be issued by the xtal oscillator or by the rc oscillator (bit selxtal in reguartcmd ). the following rc frequencies are suitable for correct uart protocols. the internal prescaler of the uart has to be set according to the rc frequency : note: the bit uartrcsel[2:0] in reguartcmd only sets the internal prescaler of the uart. it has no influence on the rc oscillator trimming or on the cpu prescaler. 9.4 function description the bit uarttxfull in reguarttxsta goes to 0 when the uart transfers data from the reguarttx register to the transmitter shift register, and goes to 1 when the processor writes new data onto the reguarttx . an interrupt is generated when there is a falling edge of the uarttxfull bit. rc freq [hz] 9830400 4915200 2457600 1228800 614400 table 9.1: rc frequencies for uart uartrcsel[2:0] prescaler division rc freq [hz] 111 reserved 110 reserved 101 reserved 100 : 16 9830400 011 : 8 4915200 010 : 4 2457600 001 : 2 1228800 000 no division 614400 table 9.2: uart internal prescaler 9 universal asynchronous receiver/transmitter (uart) xx-xe88lc01/03/05, data book page 78 20001101 preliminary in f ormation the bit uarttxbusy in reguarttxsta shows that the transmitter has transmitted data. the bit uartrxfull in reguartrxsta goes to 1 when the uart transfers data from the receiver shift register to re- guartrx , and goes to a 0 when the processor reads the reguartrx . an interrupt is generated when there is a rising edge of the uartrxfull bit. the bit uartrxbusy in reguartrxsta shows that the receiver has received data. the bit uartrxserr in reguartrxsta shows that a start error has been detected. the bit uartrxperr in reguartrxsta shows that a parity error has been detected. the received parity is not equal to the calculated parity with the received data. the bit uartrxferr in reguartrxsta shows that a frame error has been detected. there is no stop bit. the bit uartrxoerr in reguartrxsta shows that an overrun error has been detected. the reception buffer is not empty when a new data is received. this bit is cleared by all reset conditions and by writing any data to its address. the bit uartecho in reguartctrl is used to return the rx signal on the tx signal. tx = rx xor uartxrx xor uartx- tx. uartenrx (register reguartctrl bit 6) must be zero if the reception of data in echo mode is not wanted. the bits uartenrx and uartentx in reguartctrl are used to enable or disable the reception and transmission. the bits uartxrx and uartxtx in reguartctrl are used to enable or disable the reversal on the rx and tx signal. the bits uartbr in reguartctrl are used to select the internal baudrate. the reguartcmd register is used to select the word length (7-8 data bit) uartwl , the enable or disable parity uartpe and the parity mode (odd or even) uartpm . 9.5 interrupt or polling there are two possibilities for transmit or receive a message. first by interrupt, when the reguartrx is full an interrupt is generated, the uartrx register must be read. and when the reguarttx is empty an interrupt is generated too, the uarttx register can be load. second by polling, reading and checking the uartrxfull bit and when it is at 1 the reguartrx register must be read. also, reading and checking the uarttxdfull bit and when it is 0 the reguarttx register can be load. 9.6 software hints example of programme for a transmission with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit wordlen, odd par- ity, 9600 baud, enable uart transmission). 2. write a byte in reguarttx . 3. wait on the uarttxfull bit in reguarttxsta register equal 0. 4. jump to 2 for writing the next byte if the message is not finished. 5. end of transmission. example of program for a transmission with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit wordlen, odd par- ity, 9600 baud, enable uart transmission). 2. write a byte in reguarttx . 3. when there is an interrupt, if the message is not finished then write the next byte in reguarttx else end of transmission. example of program for a reception with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit wordlen, odd par- xx-xe88lc01/03/05, data book 9 universal asynchronous receiver/transmitter (uart) 20001101 page 79 preliminary information ity, 9600 baud, enable uart reception). 2. wait on the uartrxfull bit in reguartrxsta register equal 1. 3. reading the reguartrxsta and checking if there is no error. 4. read data in reguartrx . 5. if data is not equal at end-of-line then jump to 5. 6. end of reception. example of program for a reception with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit wordlen, odd par- ity, 9600 baud, enable uart reception). 2. when there is an interrupt jump to 3 3. reading the reguartrxsta and checking if there is no error. 4. read data in reguartrx . 5. if data is not equal at end-of-line then jump to 2. 6. end of reception. uartbr[2-0] baud rate, rc input baud rate, xtal input 111 38400 - 110 19200 - 101 9600 - 100 4800 - 011 2400 2400 010 1200 1200 001 600 600 000 300 300 table 9.3: baud rate selection uartwl word length 1 8 bits 0 7 bits table 9.4: word length uartpm parity mode 1 even 0odd table 9.5: parity mode uartpe parity enable 1 with parity 0no parity table 9.6: parity enable clock/16 figure 9.1: example of uart messages bit 0 start stop bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity rx / tx start bit 0 bit 1 bit 2 bit 2 9 universal asynchronous receiver/transmitter (uart) xx-xe88lc01/03/05, data book page 80 20001101 preliminary in f ormation register name address (hex) reguartctrl h0050 reguartcmd h0051 reguarttx h0052 reguarttxsta h0053 reguartrx h0054 reguartrxsta h0055 table 9.7: uart registers uartecho echo 1echo rx -> tx 0 no echo table 9.8: echo modes bit name reset rw description 7 selxtal 0 resetsystem r w select input clock; 0->rc, 1->xtal 6 uartwakeup 0 resetsystem r w uart reception enabled on falling on rx 5-3 uartrcsel[2:0] 000 resetsystem r w rc prescaler selection 2 uartpm 0 resetsystem r w select parity mode 1 uartpe 0 resetsystem r w enable parity 0 uartwl 1 resetsystem r w select word length table 9.9: reguartcmd bit name reset rw description 7 uartecho 0 resetsystem r w enable echo mode 6 uartenrx 0 resetsystem r w enable uart reception 5 uartentx 0 resetsystem r w enable uart transmission 4 uartxrx 0 resetsystem r w invert pad rx 3 uartxtx 0 resetsystem r w invert pad tx 2-0 uartbr[2-0] 101 resetsystem r w select baud rate table 9.10: reguartctrl bit name reset rw description 7-0 uartrx xxxxxxxx r data received table 9.11: reguartrx bit name reset rw description 7-6 -- 00 r unused 5 uartrxserr x r start error 4 uartrxperr x r parity error 3 uartrxferr x r frame error 2 uartrxoerr 0 resetsystem c overrun error cleared by writing reguartrxsta 1 uartrxbusy 0 resetsystem r uart is busy receiving 0 uartrxfull 0 resetsystem r reguartrx is full (irq on full) cleared by reading reguartrx table 9.12: reguartrxsta bit name reset rw description 7-0 uarttx 00000000 resetsystem r w data to send table 9.13: reguarttx xx-xe88lc01/03/05, data book 9 universal asynchronous receiver/transmitter (uart) 20001101 page 81 preliminary information bit name reset rw description 7-2 -- 000000 r unused 1 uarttxbusy 0 resetsystem r uart is busy transmitting 0 uarttxfull 0 resetsystem r reguarttx is full (irq on empty) set by wrinting reguarttx table 9.14: reguarttxsta 9 universal asynchronous receiver/transmitter (uart) xx-xe88lc01/03/05, data book page 82 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 10 universal synchronous receiver/transmitter (usrt) 20001101 page 83 preliminary information 10 universal synchronous receiver/transmitter (usrt) 10.1 overview the xe8000 includes hardware to support the software implementation of several bidirectional synchronous serial interfaces, for master and slave modes. the serial transceiver hardware is connected to pb[5] (sin: synchronous input), pb[3] (sou: synchronous output) and pb[4] (scl: synchronous clock). the register regusrtsin can be used to read sin when the serial interface is in receive = slave mode. it is ad- vised to read the sin when in slave mode from the regusrtdata register (data is stored on scl rising edge in this register). the regusrtscl register is used to read scl when interface is in receive mode or to drive scl by writing it when in transmit mode. 10.1.1 enabling the serial interface the bit enableusrt in regusrtctrl is used to enable the serial interface and controls the sin and scl lines. this bit puts these two portb lines in open drain configuration. if no external sin and scl pull-ups are added, the user has to add them by software by setting pbpullup[5 ] and pbpullup[4] in regpbpullup (see chapter parallel io ports ). 10.1.2 reading the serial interface the bit usrtdata in regusrtdata is the prefered way to read the sin data line because this data is stored on the rising edge of the scl and will change only on the next rising scl edge. the bit usrtedgescl in regusrtedgescl is set to one on scl rising edge and is cleared on any reset as well as by reading the data from the regusrtdata . it is the prefered way of knowing if data has been stored. 10.2 registers register name address (hex) regusrtsin h0060 regusrtscl h0061 regusrtctrl h0062 reserved h0063 reserved h0064 regusrtdata h0065 regusrtedgescl h0066 reserved h0067 table 10.1: serial interface registers bit name reset rw description 7-1 reserved 0000000 r reserved 0 usrtsin 1 resetsystem r w serial data (sin on pad pb[5]) table 10.2: regusrtsin 10 universal synchronous receiver/transmitter (usrt) xx-xe88lc01/03/05, data book page 84 20001101 preliminary in f ormation bit name reset rw description 7-1 reserved 0000000 r reserved 0 usrtscl 1 resetsystem r w serial clock (scl on pad pb[4]) table 10.3: regusrtscl bit name reset rw description 7-3 reserved 00000 r reserved 2-1 reserved 00 r w reserved, should always be set to 0 0 usrtenable 0 resetsystem r w enable hardware and pads for usrt (0=disable) table 10.4: regusrtctrl bit name reset rw description 7-1 reserved 0000000 r reserved 0 usrtdata x r last received data table 10.5: regusrtdata bit name reset rw description 7-1 reserved 0000000 r reserved 0 usrtedgescl 0 resetsystem r edge detection on scl (1 = edge detected) cleared by reading regusrtdata table 10.6: regusrtedgescl xx-xe88lc01/03/05, data book 11 counters/timers 20001101 page 85 preliminary information 11 counters/timers 11.1 introduction they are several types of counters in the xe8000: ?watchdog ? 4 general purpose counters/timers ? prescaler the watchdog is a counter that sends an interrupt when it is not correctly addressed within a given time. it is used to recover from abnormal situations, like endless software loops. the general purpose counters/timers are used for counting events, counting time, measuring frequency (capture function) and generating analog-like outputs (pwm). the prescaler (see prescaler on page 63) is used to extract all necessary signals from the different clocks. 11.2 watchdog watchdog is a timer which has to be cleared at least every 4 seconds by the software to prevent program overrun. the watchdog can be enabled by software, and it is disabled at power-on. once enabled, it cannot be disabled by software (only with power-on reset). see register regsysctrl (bit enreswd ). the watchdog is made of a 3 stage divider chain clocked by a 2 hz signal from the prescaler and gives a system reset if not cleared within 4 seconds. the watchdog timer can be cleared by writing two successive wdkeys to reg- syswd register. this sequence must be respected. only writing hxa followed by hx3 resets the wd. example : move addrregsyswd, #0x0a move addrregsyswd, #0x03 if some other write instruction is done to regsyswd between the hxa and hx3, the watchdog timer will not be reset. it is possible to read the status of the regsyswd register. the watchdog timer doesnt perform a full range count for the 4 bits associated with it. the watchdog is a 4 bit counter, however the count range is 0 to 7 and following the count of 7, the system reset is generated concurrently with the setting of wdcount[3] . 11.3 counters 11.3.1 overview there are four general purpose 8-bit wide up/down counters, countera, counterb, counterc & counterd. bit name reset rw description 7-4 -- 0 r reserved 3 wdkey[3] w watchdog key bit 3 wdcounter[3] 0 resetpor r watchdog counter bit 3 (1/4 hz) 2 wdkey[2] w watchdog key bit 2 wdcounter[2] 0 resetpor r watchdog counter bit 2 (1/2 hz) 1 wdkey[1] w watchdog key bit 1 wdcounter[1] 0 resetpor r watchdog counter bit 1 (1 hz) 0 wdkey[0] w watchdog key bit 0 wdcounter[0] 0 resetpor r watchdog counter bit 0 (2 hz) table 11.1: regsyswd 11 counters/timers xx-xe88lc01/03/05, data book page 86 20001101 preliminary in f ormation each counter has four possible clock inputs. three of them are internal clocks provided by the prescaler and the forth is a porta pin. the clock input of porta is set as a normal porta input (rising/falling, debounced/not debounced). countera and counterb can be combined to form a 16-bit counter and similarly with counterc and counterd. when not in pwm mode, counters can generate an interrupt when reaching a predefined value. counters can also be used to generate two pwm outputs on pb[1] and pb[0]. in pwm mode one can generate pwm functions on 8 to 16 bits width. note: if powerxtal is set when the counter is set to use one of the low frequency clocks (32khz or lower), counter switches immediately on xtal. the xtal frequency takes time to stabilize. coldxtal goes low when the xtal is considered stable. additionally, the low 15-stage divider of the prescaler is cleared when powerxtal is set. 11.3.2 features ? four independent 8-bit up/down counters - each with 4 possible clock selections ? pa[3:0] can be used as clock inputs (debounced or direct) ? counters can be set in pairs to form blocks of 16-bit counters ? generate interrupts when used as normal counters ? pwm function on two simple (8-bit) or combined (16-bit) counters. ? pwm function on 8 / 10 / 12 / 14 / or 16 bit width ? capture function (internal or external) ? pwm output on pb[1] and pb[0] 11.3.3 block schematics 11.3.4 counter registers counters are enabled by cntaenable , cntbenable , cntcenable , cntdenable in regcnton . each counter has a corresponding 8 bit read/write register regcnta , regcntb , regcntc , and regcntd . these registers contain the counter value for the purposes of reading. when written by the user, they contain the compar- ison values. they can only be reliably modified when the counter is stopped. figure 11.1: counters/timers block schematics counter a regcnta counter b regcntb counter c regcntc counter d regcntd ck128 ck250k ck1m pa(0) capture ck128 ck250k ck1m pa(1) ck128 ck1k ck32k pa(2) ck128 ck1k ck32k pa(3) ck1k pa(2) ck32k pa(3) xx-xe88lc01/03/05, data book 11 counters/timers 20001101 page 87 preliminary information to stop the counter, cnt x enable must be reset. to start the counter, cnt x enable must be set. the only operation allowed when the counter is stopped is loading the counter with data. if no new data has been written, the counter remains unchanged. so the smallest sequence is a stop/modify/start. it is possible to read any counter at any time, even when the counter is running. however, the value is only guaran- teed correct when the counter is static. for precise counter acquisition, one should use the capture function (see below). 11.3.5 clock selection the clock source for each counter can be individually selected by writing the appropriate value in regcntctrlck . each value can be 1 of 4 (2 bits) : each represents one of the different clock options. table 7.1, 7.2, 7.3 & 7.4 de- scribe the code for each counter clock source combination. see chapter prescaler on page 63, and figure 7.4 for more explainations about the ck128, ck1k, ck32k, ck250k, and ck1m signals. the clock source must be changed only when the counter is stopped. once the counter is restarted/ started, the circuit wait for a falling edge on the clock signal (internally generated clock or external source), to start counting. the counter is modified at the clock rising edge. depending when the start of the counter related to its selected clock arrives, the first counter clock might not be counted because the first falling edge is used for synchronization and counter preparation. cntacksel[1:0] clock source 11 ck128 10 ck250k 01 ck1m 00 pa[0] table 11.2: clock source for counter a cntbcksel[1:0] clock source 11 ck128 10 ck250k 01 ck1m 00 pa[1] table 11.3: clock source for counter b cntccksel[1:0] clock source 11 ck128 10 ck1k 01 ck32k 00 pa[2] table 11.4: clock source for counter c cntdcksel[1:0] clock source 11 ck128 10 ck1k 01 ck32k 00 pa[3] table 11.5: clock source for counter d 11 counters/timers xx-xe88lc01/03/05, data book page 88 20001101 preliminary in f ormation when the counter arrives at irq condition (if count down when it change to 00), it does not give an irq at that mo- ment but one half period of selected clock later. if corresponding countermask bits are set to 1, interrupts are generated on the clocks falling edge after the counter has reached the expected value. the counter is stopped immediately by setting start at 0. if a rising edge occurs exactly at this time, we cannot predict if the counter will be modified or not. for this reason, there is always a 1 lsb uncertainty on the counter value. note: you can read the counter properly only when the counter is stopped. reading on run can give false values. this case is not advised, use only when the counter counts at least 8 times lower than cpu clock. in this case user can do a software filer of at least three readings to determine the counter value. be careful to select the counter mode before writing any value in it. value is not stored in the counter in the up-count mode. in down-count or pwm mode, the value is stored in the counter. when you write a value into the counter, the counter will be cleared if you are in up-count mode. otherwise, the counter will be loaded with the value. if you do not write a value, the counter will not be modified, even if you are modifying the mode. 11.3.6 16 bit counters cascadeab and cascadecd in regcntconfig1 are used to set the count ranges. when cascadeab is set, the countera is connected to counterb to form a 16-bit wide counter. in this case, coun- tera is the lsb and counterb is the msb. when not cascaded (cascadeab = 0), the counters are independent. counterc and counterd can be set similarly with cascadecd . there is no default values, so these bits must be set before using any of the counters. cascadeab counters 1 16 bits counter ab 0 8 bit counter a 8 bit counter b table 11.6: cascading counter a & b counter 2 clock figure 11.2: start synchronization 1 0 enable the counter counter interrupt n-1 clock figure 11.3: interrupt generation n 0 1 xx-xe88lc01/03/05, data book 11 counters/timers 20001101 page 89 preliminary information only countera and counterc irq are generated in 16 bit mode. 11.3.7 up/down counting the counters can be up- or down-counting. 11.3.7.1 up-counting for 8 bits up-counting, we see the following behaviour: ? counter a: 0,1,2,...,valuea-1,valuea,0,1,....,valuea-1,valuea,... ? counter b: 0,1,2,...,valueb-1,valueb,0,1,....,valueb-1,valueb,... for 16 bits up-counting, we see the following behaviour: ? counter (b,a): (00, 00), (00, 01),..., (00, ff), (01, 00), (01, 01), .., (valueb, valuea), (00,00), ... in 16 bits mode, counter b is incremented only when counter a is ff irq generated when counter reaches value. 11.3.7.2 down-counting for 8 bits down-counting, we see the following behaviour: ? counter a: valuea,...,2,1,0,valuea,valuea-1,....,2,1,0,valuea,... ? counter b: valueb,...,2,1,0,valueb,valueb-1,....,2,1,0,valueb,... for 16 bits down-counting, we see the following behaviour: ? counter (b,a): (valueb, valuea), (valueb, valuea-1),..., (valueb, 00), (valueb-1, ff), .., (00,00), (valueb, val- uea), ... irq generated when counter reaches 0. 11.3.7.3 registers for up/down counting cntadownup , cntbdownup , cntcdownup & cntddownup in regcntconfig1 are used to individually set up and down counting for counters a, b ,c & d. note: there is no default values, so these bits must be set before using any of the counters. an irq will be generated every value+1 clock cycles for example in 8 bits mode, if you load the counter with a value h5b, with a 4 mhz clock, an interrupt will be generated every 23 us; in 16 bits mode, if you load the counter will a value h5ba7, with a 4 mhz clock, an interrupt will be generated every 5866 us. cascadecd counters 1 16 bits counter cd 0 8 bit counter c 8 bit counter d table 11.7: cascading counter c & d cntxdownup counterx 1 up-counting 0 down-counting table 11.8: selection for up/down-counting 11 counters/timers xx-xe88lc01/03/05, data book page 90 20001101 preliminary in f ormation 11.3.8 capture functions 11.3.8.1 overview the 16 bit capture register is provided to facilitate frequency measurements. it captures the data held in counters a and b and is split into capturea and captureb. the instant of capture for both capturea and captureb are user defined by selecting either internal sources derived from the prescaler or from a chip pin (pa[2] or pa[3]). both reg- isters use the same capture source. for all sources, rising edge sensitivity, falling edge sensitivity or both can be selected dynamically. this is especially useful for synchronizing with signals for which duty cycle measurements are required. the source of the capture signal and the edge sensitivity are determined in regcntconfig2 . when counters a or b are active, reads performed on their associated addresses come from the capture register. figure 11.5 shows a representation of the capture block within the context of counter a. pwm clock down-counter up-counter figure 11.4: counter examples 0 2 1 n-1 n 0 1 2 n-1 n 0 1 n n-2 n-1 1 0 n n-1 n-2 1 0 n n-1 pwm counter 0 fe ff n+1 n n-1 n-2 n-3 1 0 ff fe figure 11.5: capture architecture (counter a) edge detector (1) capture source select edge detector (2) cpu clock capture function counter a irq counter a data out counter a clock temp copy of a cpudomain copy of a counter/capture block data a output irq counter/capture a ck1k ck32k pa(3) pa(2) capture edge select xx-xe88lc01/03/05, data book 11 counters/timers 20001101 page 91 preliminary information 11.3.8.2 detailed implementation several edge detectors and temporary registers are implemented to ensure proper operation of the capture function despite the asynchronous multiple clocks. understanding of the detailed implementation is only required for very precise measurements. other users may directly go to the registers chapter. when in capture mode the capture block becomes the source of interrupts from the counter/capture block a. addi- tionally, the global data register address associated with the counter/capture block a becomes that labelled as cpu- domain copy of a within the figure. within the capture architecture there are two edge detector blocks, namely: ? edge detector (1) ? edge detector (2) edge detector (1) generates the strobe pulse that captures the contents of the counter into the register marked temp copy of a within figure 11.5. this strobe signal is also used to communicate the availability of data within that reg- ister to the edge detector (2) block which in turn generates the strobe signal that copies the data into the cpu clock domain. the architectures of edge detector (1) and edge detector (2) are represented in figure 11.6 and figure 11.7 respec- tively. the edge detector (1) represented in figure 11.6 may be divided into two sections that are associated with rising edge detection (top row of cells) and falling edge detection (bottom row of cells). to explain the circuit functionality the rising edge detection is used as an example. the state of enable rising is user defined. assuming that it is dis- abled (set to 0) then no contribution is made to the latch enable output circuit. if the enable rising signal is active (set to 1), then the output of d-flip-flop a (subsequently referred to as a ) becomes high within a flip-flop delay time of the rising edge of the capture signal. this signal remains until a is reset. following the next falling edge of the clock signal, the output of a is copied to b . the next rising edge of clock copies this further to c . the output of c causes a to be reset; only to become active following the detection of the next rising edge of the capture signal (if enabled). this structure is based on conventional techniques for exchanging data be- tween different clock domains. within the bottom row of cells, d is sensitive to the falling edge of capture. figure 11.6: edge detector (1) principle clock enable capture enable rising falling latch enable a b c d 11 counters/timers xx-xe88lc01/03/05, data book page 92 20001101 preliminary in f ormation the behavior of the edge detector (2) is similar to that previously described, with the exception that it is always en- abled and the output of cell a is always set following the rising edge of the flip flop generated by edge detector (1). in both circuits, the outputs of cells a and d can only be reset (during normal operation) as a result of acknowledg- ment of the request signal ( a or d ) by downstream cells. 11.3.8.3 registers table 11.9 and table 11.10 describe the mapping between the codes placed on capsel[1:0] (capture source se- lect) and capfunc[1:0] (capture function) and their meanings. 11.3.9 pwm functions 11.3.9.1 general the counters can generate pwm (pulse width modulation) pb(0) and pb(1) outputs. pwm mode override normal outputs settings on pb(0) and pb(1) (except analog mode). the counters can be used in 8 or 16 bits mode. counters in pwm mode always count down, independently of cntx- downup setting. capsel[1:0] source 11 ck1k (rc divider) 10 ck32k (rc divider) 01 pa[3] 00 pa[2] table 11.9: capture source capfunc[1:0] selection 11 both edges 10 falling edge 01 rising edge 00 disabled table 11.10: capture function selection figure 11.7: edge detector (2) principle clock capture 1 latch enable a xx-xe88lc01/03/05, data book 11 counters/timers 20001101 page 93 preliminary information output is low as long as the value of the counter is bigger than the stored value, and high when the value of the counter is smaller or equal to the stored value. cntpwm1 and cntpwm0 in regcntconfig1 are used to set pwm functions. these two bits are by default after any reset cleared to 0 disabling the pwm function. pwm resolution is always 8 bits when the counters are in 8 bits mode. pwm1size and pwm0size in regcntconfig2 are used to set the pwm resolution when the counters are in 16 bits mode ( cascadeab or/and cascadecd set). note: counters used for pwm do not generate any irq. 11.3.9.2 pwm in 8 bits mode with value in the range from 0 - ff one selects the duty cycle of the output between 0 and 99.6%. h00 = 0%, h3f = 25%, h7f = 50%, hff = 255/256. 11.3.9.3 pwm in 16 bits mode the counter counts from 0, max, max-1, ....., 2, 1, 0, max, max-1, ....... max is depending on the pwm size setting. it is hffff for 16 bits, h3fff for 14 bits, h0fff for 12 bits and h03ff for 12 bits. cntpwm1 pwm1 pb[1] 1 active outputs pwm1 0 stopped normal function table 11.11: pwm1 cntpwm0 pwm0 pb[0] 1 active outputs pwm0 0 stopped normal function table 11.12: pwm0 pwm1size[1:0] size of pwm1 11 16 bits 10 14 bits 01 12 bits 00 10 bits table 11.13: pwm1 size selection pwm0size[1:0] size of pwm0 11 16 bits 10 14 bits 01 12 bits 00 10 bits table 11.14: pwm0 size selection small stored value big stored value figure 11.8: pwm output examples 11 counters/timers xx-xe88lc01/03/05, data book page 94 20001101 preliminary in f ormation 11.3.10 counter registers register name address (hex) regcnta h0058 regcntb h0059 regcntc h005a regcntd h005b regcntctrlck h005c regcntconfig1 h005d regcntconfig2 h005e regcnton h005f table 11.15: counters registers bit name reset rw description 7-0 countera xxxxxxxx r w 8-bit counter a table 11.16: regcnta bit name reset rw description 7-0 counterb xxxxxxxx r w 8-bit counter b table 11.17: regcntb bit name reset rw description 7-0 counterc xxxxxxxx r w 8-bit counter c table 11.18: regcntc bit name reset rw description 7-0 counterd xxxxxxxx r w 8-bit counter d table 11.19: regcntd bit name reset rw description 7-6 cntdcksel[1:0] xx r w counterd clock selection 5-4 cntccksel[1:0] xx r w counterc clock selection 3-2 cntbcksel[1:0] xx r w counterb clock selection 1-0 cntacksel[1:0] xx r w countera clock selection table 11.20: regcntctrlck bit name reset rw description 7 cntddownup x r w counterd down- or up-counting (0=down) 6 cntcdownup x r w counterc down- or up-counting (0=down) 5 cntbdownup x r w counterb down- or up-counting (0=down) 4 cntadownup x r w countera down- or up-counting (0=down) 3 cascadecd x r w cascade counter c & counter d (1=cascade) 2 cascadeab x r w cascade counter a & counter b (1=cascade) 1 cntpwm1 0 resetsystem r w activate pwm1 on counter c or c+d (pb[1]) 0 cntpwm0 0 resetsystem r w activate pwm0 on counter a or a+b (pb[0]) table 11.21: regcntconfig1 bit name reset rw description 7-6 capsel[1:0] 00 resetsystem r w capture source selection 5-4 capfunc[1:0] 00 resetsystem r w capture function table 11.22: regcntconfig2 xx-xe88lc01/03/05, data book 11 counters/timers 20001101 page 95 preliminary information 3-2 pwm1size[1:0] xx r w pwm1 size selection 1-0 pwm0size[1:0] xx r w pwm0 size selection bit name reset rw description 7-4 -- 0000 r reserved 3 cntdenable 0 resetsystem r w enable counter d 2 cntcenable 0 resetsystem r w enable counter c 1 cntbenable 0 resetsystem r w enable counter b 0 cntaenable 0 resetsystem r w enable counter a table 11.23: regcnton bit name reset rw description table 11.22: regcntconfig2 11 counters/timers xx-xe88lc01/03/05, data book page 96 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 12 voltage level detector 20001101 page 97 preliminary information 12 voltage level detector 12.1 features ? can be switched off and on ? generates an interrupt if power supply is below a pre-determined level at end of measurement 12.2 overview the voltage level detector monitors the state of the system battery. it returns a logical value depending on the result. if the supplied voltage drops below a user defined value (vsb) then an interrupt request (1 on vldirq ) is generated. 12.3 vld operation the vld is controlled by vldmult , vldtune and vlden . vldmult selects the voltage range applicable to the product, while vldtune is used to programme the reference voltage level. vlden is used to enable (disable) the vld with a 1(0) value respectively. the user tunes the vsb level using the vldtune bits. in low and high range, 8 values of vsb can be selected. to start the voltage level detection, the user sets bit vlden . analog part is powered and measurement is started. after the measurement, bit vldvalid is set to signal validity of vldirq , a maskable interrupt request is sent if voltage level is below threshold. by reading bit vldirq , the user knows the power supply status. figure 12.1 describes the functionality of the vldvalid and vldirq signals with respect to the battery level (vbat), the measurement made by the analog part of the vld (vld_out), the vld enable signal, the vld_valid signal and the vld_irq signal.the vld is intended to be polled, namely: the user requests that a measurement be taken by vlden . the bit vldvalid becomes active indicating the validity of vldirq . once the vldirq has been read, the user can dis- able the vld by setting the vlden to 0. figure 12.1 shows that the vldvalid signal rises to its active state with the sixteenth rising ck8k edge following the rise of vlden . the intermediate time is required for the vld to stabilize. digital filtering is used to filter the output sig- nal. symbol description min typ max unit comments vsb threshold voltage for vld_tune = h100 1.2 2.4 1.3 2.55 1.4 2.7 v v low range high range dvsb step size of tuning 6 % relative to vsb t eom duration of measurement 2 ms time between setting vlden and rise of vldvalid table 12.1: voltage level detector operation vlden vld_out vldvalid vldirq vbat 56 ck8k 1234 7 1 56 1234 7 56 1234 7 56 1234 7 figure 12.1: vld timing 12 voltage level detector xx-xe88lc01/03/05, data book page 98 20001101 preliminary in f ormation figure 12.1 also shows that if the vld remains in the enabled state, it continues to generate interrupt requests as appropriate. however, it should be noted that these are based on the existence of three consecutive agreeing meas- urements being made, and therefore the transitions occuring on vldirq are not always equi-distant. 12.4 registers the cpu interface comprises two 8 bit registers that are globally accessible, namely regvldctrl and regvldstat . table 12.2 shows the mapping of control bits and functionality of regvldctrl while table 12.3 describes that for regvldstat . bit name reset rw description 7-4 -- 0000 r reserved 3 vldmult 0 resetcold r w vld double level dectector 2-0 vldtune[2:0] 000 resetcold r w vld level tuning table 12.2: regvldctrl bit name reset rw description 7-3 -- 00000 r reserved 2 vldirq 0 resetsystem r vld irq 1 vldvalid 0 resetsystem r vld valid result 0 vlden 0 resetsystem r w vld enable table 12.3: regvldstat xx-xe88lc01/03/05, data book 13 power-on reset 20001101 page 99 preliminary information 13 power-on reset the power-on reset (por) block fixes the conditions for the beginning of the power-on sequence (see system chapter). at start-up of the circuit, the por block generates a reset signal during t on . in normal mode if the voltage supply falls below a critical value, the reset signal is activated. note: 1) threshold voltage for the power-on reset does not imply that this voltage is sufficient for correct operation of the cpu. this has to be checked with the voltage level detector during operation of the device, and to be ensured by design for the start-up of the chip. note: 2) the vdd_sl defines a minimum slope on vreg. the power-on reset behaviour of the circuit is not guar- anteed if this slope is too slow as system could start before program memory has sufficient voltage to insure correct behaviour. in such a case, a delay has to be built using the reset pin. note: 3) the power-on sequence (see system chapter) follows the reset duration. symbol description min typ max unit comments t on reset duration 5 20 ms 3 t drop drop duration 10 m s v f = 0.4 vreg v t start threshold voltage 0.7 1.1 v 1 vdd_sl_m voltage slope for activation of mtp versions 20 v/ms 2 vdd_sl_r voltage slope for activation of rom versions 0.25 v/ms 2 table 13.1: por specifications figure 13.1: reset conditions vreg por v t v f t rise t on t drop 13 power-on reset xx-xe88lc01/03/05, data book page 100 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 14 acquisition chain 20001101 page 101 preliminary information 14 acquisition chain 14.1 introduction the acquisition chain is made of an analog multiplexer (amux) entering a programmable gain amplifier (pga) followed by an analog-to-digital converter (adc). it is intended to sense a differential voltage at its input, which can be connected for instance to a wheatstone-bridge type resistive sensor, and to deliver a signed 16 bits-wide word in 2s complement. a busy signaland a maskable interrupt inform the cpu about the state of the conversion. the pga can provide both amplification and offset compensation. the adc converter is oversampled and incre- mental, i.e. it uses several input samples to generate one output data and it is reset before each conversion. its over- sampling ratio can be programmed as a power of 2 to choose the appropriate trade-off between conversion duration and resolution. input swiching is immediate when pga is off, it requires a short delay when pga is on. the block can be operated in two ways: on request upon a start conversion signal or continuously running. 14.2 block diagram figure 14.1 shows the general block diagram of the peripheral. the pga selects a combination of input signals, modulates the input voltage and amplifies it through 1 to 3 stages, 2 of these providing offset compensation. each amplifier can be bypassed. the adc delivers the output in 2s complement. the acquisition channel also includes a control block that manages all communication with the cpu, sets the configuration of the peripheral and imple- ments the different test modes. 14.3 input signal multiplexing there are 8 inputs named ac_a[0] to ac_a[7]. inputs can be used either as four differential channels (vin1=ac_a[1]-ac_a[0], , vin4=ac_a[7]-ac_a[6]) or ac_a[0] can be used as a common reference, providing 7 signal paths (ac_a[1]-ac_a[0], , ac_a[7]-ac_a[0]), all referred to ac_a[0]. default input is vin1. figure 14.1: acquisition channel block diagram with zoomingadc? gain1 offset2 gain2 offset3 gain3 mode output code input selection adc ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) ac_r(0) ac_r(1) ac_r(2) ac_r(3) reference selection zoom 14 acquisition chain xx-xe88lc01/03/05, data book page 102 20001101 preliminary in f ormation on top of these settings, inputs can be crossed or not. all multiplexing combinations are summarised in the following table (see table 14.1) : 14.4 input reference multiplexing one must select one of two differential signal as reference signal (vref1=ac_r[1]-ac_r[0], vref2=ac_r[3]- ac_r[2]). default is vref1. 14.5 amplifier chain the 3 stages transfer functions are: vd3 = gd3 . vd2 - gdoff3 . vref vd2 = gd2 . vd1 - gdoff2 . vref vd1 = gd1 . vin where: vin=selected input voltage vref=selected reference voltage vd1=differential voltage at the output of first amplifier vd2=differential voltage at the output of second amplifier vd3=differential voltage at the output of third amplifier gd1=differential gain of stage 1 gd2=differential gain of stage 2 gd3=differential gain of stage 3 gdoff2= offset gain of stage 2 gdoff3=offset gain of stage 3 and therefore the whole transfer function is: vout of pga = vd3 = gd3 . gd2 . gd1 . vin - (gdoff3 + gdoff2 . gd3) . vref note: as the offset compensation is realized together with the amplification on the same summing node. the only voltages that have to stay within the power supply are vref and the vd i . gd i (output of the amplifiers). uni/bi-polar sign channel selection selected differential input amux(4) amux(3) amux(2) amux(1) amux(0) vin- vin+ 0 0 unused 0 0 a(0) a(1) 0 1 a(2) a(3) 1 0 a(4) a(5) 1 1 a(6) a(7) 1 unused 0 0 a(1) a(0) 0 1 a(3) a(2) 1 0 a(5) a(4) 1 1 a(7) a(6) 1 0 000a(0)a(0) 001a(0)a(1) 010a(0)a(2) 011a(0)a(3) 100a(0)a(4) 101a(0)a(5) 110a(0)a(6) 111a(0)a(7) 1 000a(0)a(0) 001a(1)a(0) 010a(2)a(0) 011a(3)a(0) 100a(4)a(0) 101a(5)a(0) 110a(6)a(0) 111a(7)a(0) table 14.1: amux selection xx-xe88lc01/03/05, data book 14 acquisition chain 20001101 page 103 preliminary information vd i-1 and gdoff i . vref can be larger the the power supply without any saturation. note: all stages use a fully differential architecture and all gain and offset settings are realized with ratios of ca- pacitors. note: as the adc also provides a gain (2 nominal), the total chain transfer function is: adc_out= (2 . gd3 . gd2 . gd1 . vin/vref -2 . (gdoff3 + gdoff2 . gd3)) . (smax+1)/smax . 2 16 each stage is called pgai. features of these stages are: ? gain can be chosen between 1 and 10 (between 0 and 10 for pga3) ? offset can be compensated for in pga2 (a little) and in pga3 (to a large extent) ? granularity of settings is rough for pga1, medium for pga2, fine for pga3 ? zero, one, two or three of the pga stages can be used. a functional example of one of the stages is given on figure 14.2. 14.5.1 pga 1 note: 1) measured with block connected to inputs through amux block. normalized input sampling frequency for input impedance is 512 khz. this figure has to be multiplied by 2 for fs = 256 khz and 4 for fs = 128 khz. note: 2) input referred rms noise is 10 uv per input sample. this corresponds to 18 nv/sqrt(hz) for fs = 512 khz. 14.5.2 pga2 symbol description min typ max unit comments gd_preci precision on gain settings -5 +5 % gd_tc temperature dependency of gain settings -5 +5 ppm/c fs input sampling frequency 5 512 khz zin1 input impedance 150 k w 1 zin1p input impedance for gain 1 1500 k w 1 vn1 input referred noise 18 nv/ sqrt(hz) 2 table 14.2: pga1 performances sym description min typ max unit comments gdoff2 pga2 offset gain -1 1 fs gdoff2_step gdoff2(code+1) C gdoff2(code) 0.18 0.2 0.22 - gd_preci precision on gain settings -5 +5 % valid for gd2 and gdoff2 gd_tc temperature dependency of gain settings -5 +5 ppm/c fs input sampling frequency 5 512 khz table 14.3: pga2 performances figure 14.2: pga stage principle implementation vref vin vout 14 acquisition chain xx-xe88lc01/03/05, data book page 104 20001101 preliminary in f ormation note: 1) measured with block connected to inputs through amux block. normalized input sampling frequency for input impedance is 512 khz. this figure has to be multiplied by 2 for fs = 256 khz and 4 for fs = 128 khz. note: 2) input referred rms noise is 26uv per sample.this corresponds to 36 nv/sqrt(hz) max for fs = 512 khz. 14.5.3 pga3 note: 1) measured with block connected to inputs through amux block. normalized input sampling frequency for input impedance is 512 khz. this figure has to be multiplied by 2 for fs = 256 khz and 4 for fs = 128 khz. note: 2) input referred rms noise is 26uv per sample. this corresponds to 36 nv/sqrt(hz) max for fs = 512 khz. 14.6 adc 14.6.1 input-output relation the adc block is used to convert the differential input signal into a 16 bits 2s complement output format. the output code corresponds to the ratio: smax being the number of samples used to generate one output sample per elementary conversion. smax is set by osr on regaccfg0 . vref can be selected up to the power supply rails and must be positive. the corresponding 2s complement output code is given in hexadecimal notation by 8000 (negative full scale) and 7fff (positive full scale). code outside the range are saturated to the closest full scale value. note: the output code is normalized into a 16 bits format by shifting the result left or right accordingly. 14.6.2 operation mode the mode can be either on request or continuously running. in the on request mode, after a request, an initialization sequence is performed, then an algorithm is applied and an output code is produced. the converter is idle until the next request. in the continuously running mode, an internal conversion request is generated each time a conversion is finished, so that the converter is never idle. the output code is updated at a fixed rate corresponding to 1/tout, with tout being the conversion time. zin2 input impedance 150 k w 1 vn2 input referred noise 36 nv/ sqrt(hz) 2 sym description min typ max unit comments gdoff3 pga3 offset gain -5 5 fs gd3_step gd3(code+1) - gd3(code) 0.075 0.08 0.085 - gdoff3_step gdoff2(code+1) C gdoff2(code) 0.075 0.08 0.085 - gd_preci precision on gain settings -5 +5 % valid for gd3 and gdoff3 gd_tc temperature dependency of gain settings -5 +5 ppm/c fs input sampling frequency 5 512 khz zin3 input impedance 150 k w 1 vn3 input referred noise 36 nv/ sqrt(hz) 2 table 14.4: pga3 performances sym description min typ max unit comments table 14.3: pga2 performances output code = 2 * vin(adc) vref smax + 1 smax . . 2 16 xx-xe88lc01/03/05, data book 14 acquisition chain 20001101 page 105 preliminary information 14.6.3 conversion sequence the whole conversion sequence is basically made of an initialisation, a set of n umconv elementary incremental con- versions and finally a termination phase ( n umconv is set by the 2 nelconv bits on regaccfg0 ). the result is a mean of the results of the elementary conversions. note: n umconv elementary conversions are performed, each elementary conversion being made of smax input samples. n umconv = 2 nelconv smax = 8 * 2 osr during the elementary conversions, the operation of the converter is the same as in a sigma delta modu- lator. during one conversion sequence, the elementary conversions are alternatively performed with direct and crossed pga-adc differential inputs, so that when two elementary conversions or more are per- formed, the offset of the converter is cancelled. note: the sizing of the decimation filter puts some limits on the total number of conversions and it is not possible to combine the maximum number of elementary conversions with the maximum oversampling (see the nel- conv*smax specification). some additional clock cycles (n init +n end ) clock cycles are required to initiate and terminate the conversion prop- erly. 14.6.4 conversion duration the conversion time is given by : t out = (n umconv * smax + 1 + n init + n end ) / fs 14.6.5 resolution as far as it is not limited by thermal noise and internal registers width, the resolution is given by : resolution (in bits) = 6 + 2 * osr + nelconv 14.6.6 adc performances sym description min typ max unit comments vinr input range -0.5 0.5 vref resol resolution 12 bits 1 nresol numerical resolution 16 bits 4 inl integral non-linearity 4 lsb 1,3, lsb at 12bits tc temperature dependency of sensitivity -5 +5 ppm/c fs sampling frequency 10 512 khz table 14.5: adc performances figure 14.3: conversion sequence. smax is the oversampling rate. start end 1st elementary conversion 2nd elementary conversion elementary conversion elementary conversion conversion index 1 2n umconv -1 n umconv input 12 smax 12 smax 12 smax sample 14 acquisition chain xx-xe88lc01/03/05, data book page 106 20001101 preliminary in f ormation note: 1) resolution specification also includes thermal noise and differential non-linearity (dnl) for a reference signal of 2.4 v. it is defined for default operating mode ( see default operation mode (not yet implement- ed) on page 106.) note: 2) only powers of 2 note: 3) inl is defined as the deviation of the dc transfer curve from the best fit straight line. this specification holds over the full scale. note: 4) nresol is the maximal readable resolution of the digital filter. input noise may be higher than nresol. 14.7 control part 14.7.1 starting a convertion a conversion is started each time start or def is set. pgas are reset after each writing operation to registers regaccfg1-5 . the adcs must be started after a pga com- mon-mode stabilisation delay. this is done by writing bit start several cycles after pga settings modification. de- lay between pga start and adc start should be equivalent to smax number of cycles. (this delay does not apply to conversions made without the pgas) 14.7.2 clocks generation the clock of the acquisition path is derived from the rc oscillator clock. fs = psck/4 psck can be chosen among four prescaler clocks (bit fin of regaccfg2 ), see table 14.7. 14.7.3 default operation mode (not yet implemented) the def bit ( regaccfg5 ) allows the use of the adc in a default mode without any gain nor offset adjustment (see values in the right column of table 14.7). the only action to launch the adc default conversion is to write a b01aaaaav in regaccfg5 , aaaaa being the amux selection and v the vmux selection. this default mode is used in specifications to define resolution and inl. 14.7.4 registers eight registers control this peripheral. two registers are for the data output, six for peripheral general set-up. reg- isters are defined in table 14.6 and table 14.7. smax oversampling ratio 8 1024 - 2 n umconv number of elementary conversions 1 8 - 2 ninit number of periods for incremental conversion initialization 5- nend number of periods for incremental conversion termination 5- register data regacoutlsb adc_out_l regacoutmsb adc_out_h regaccfg0 start nelconv osr cont reserved regaccfg1 ib_amp_adc ib_amp_pga enable regaccfg2 fin pga2_gain pga2_off regaccfg3 pga1_ gain pga3_gain regaccfg4 reserved pga3_off regaccfg5 busy def amux vmux table 14.6: peripheral register memory map sym description min typ max unit comments table 14.5: adc performances xx-xe88lc01/03/05, data book 14 acquisition chain 20001101 page 107 preliminary information name register rm description default (reset and def mode) adc_out(15:0) regacoutlsb regacoutmsb r data output data is shifted left for having the msb on the msb of regacoutmsb for any resolution. therefore lsbs may be fixed at 0 ifdigital resolution is below 16 bits. 0000h amux(4:0) regaccfg5 wr selection of pga inputs 00000 (reset only) busy regaccfg5 r 1 : conversion is in progress 0 : data is available 0 cont regaccfg0 wr 1 : continuous operation. 0 : one shot mode 0 def regaccfg5 wr0 default operation bit (not yet implemented) 1: all registers but vmux and amux are reset and default values are used 0: normal operation n/a enable(3:0) regaccfg1 wr bit3 : pga3, bit2 : pga2, bit1 : pga1, bit 0 : adc if a bit is 1, the block is powered. if not, the block is switched off and all internal digital signals are reset. concerning the pgas, enable=0 means also that inputs and outputs are wired together and that the acquisition chain is not perturbed by the block. 0000 (reset) 0001 (def mode) fin(1:0) regaccfg2 wr 00 : rc is used as master clock (psck) 01 : rc / 2 is used as master clock (psck) 10 : rc / 8 is used as master clock (psck) 11 : rc / 32 is used as master clock (psck) rem: do not select a clock that results in fs faster than 512 khz. 00 ib_amp_pga(1:0) regaccfg1 wr pga amplifiers biasing current reduction factor 00 : current = 0.25 nominal current 01 : current = 0.5 nominal current 10 : current = 0.75 nominal current 11 : current = nominal current 11 ib_amp_adc(1:0) regaccfg1 wr adc amplifiers biasing current reduction factor. tuning identical to ib_amp_pga 11 nelconv(1:0) regaccfg0 wr number of elementary conversions setting 00 : 1 conversion, 01 : 2 conversions 10 : 4 conversions, 11 : 8 conversions 01 osr(2:0) regaccfg0 wr oversampling ratio setting. defined as fs/fout. smax = 8*2 osr(2:0) . 000 : oversampling = 8, ..., 111 : oversampling = 1024 010 pga1_gain regaccfg3 wr signal gain of first pga stage (gd1) 1 : nominal gain is 10. 0 : nominal gain is 1 0 pga2_gain(1:0) regaccfg2 wr signal gain of second pga stage (gd2) 11 : nominal gain is 10 10 : nominal gain is 5 01 : nominal gain is 2 00 : nominal gain is 1 00 pga2_off(3:0) regaccfg2 wr offset gain of second pga stage (gdoff2) bit 3: offset sign (0 : gdoff2 > 0, 1 : gdoff2 < 0) bits (2:0) : offset amplitude 01x1 : gdoff2 = 1.0 nominal, 0100 : gdoff2 = 0.8 nominal, 0011 : gdoff2 = 0.6 nominal, ..., 0000 : gdoff2 = 0.0 nominal, 1001 : gdoff2 = -0.2 nominal, ..., 11x1 : gdoff2 = -1.0 nominal 0000 pga3_gain(6:0) regaccfg3 wr signal gain of third stage (gd3) gd3 = 0.08*pga3_gain(6:0) nominal values : 0 (000 0000), ..., 10 (111 1000) 000 1100 pga3_off(6:0) regaccfg4 wr offset gain of third stage (gdoff3) bit 6: offset sign (0 : gdoff3 > 0, 1 : gdoff3 < 0) gdoff3 = 0.08*pga3_off(5:0), maximum = 5.04 nominal values : -5.04 (111 1111), 0 (x00 0000), +5.04 (011 1111) 000 0000 start regaccfg0 wr0 writing a 1 in start bit restarts the adc. it does not affect the pgas. 0 test regaccfg0 reserved 0 vmux regaccfg5 wr vref selection multiplexer 0 : vref0 is used, 1 : vref1 is used 0 (reset only) table 14.7: peripheral register memory map, bits description 14 acquisition chain xx-xe88lc01/03/05, data book page 108 20001101 preliminary in f ormation 14.8 acquisition of a sample figure 14.4: acquisition flow use default mode write in regaccfg5 yes no use pga write in regaccfg1-5 yes no and modifiy pga wait for pga stable start adc by writing regaccfg0 wait for adc ready read adc results xx-xe88lc01/03/05, data book 15 analog outputs 20001101 page 109 preliminary information 15 analog outputs the pwm dacs available in all xe8000 products are described in the timers chapter. the xe88lc05 has two additional digital to analog converters (dac)s: a signal dac able to pass a 4 khz signal with 10 bits precision (16 bits resolution at low frequency), and a bias dac able to output 10 ma to bias a resistive bridge sensor on 8 bits resolution. both are dacs formed from a generic dac and an amplifier. this makes possible current and voltage drive and lets full freedom for the user to choose the preferred filtering scheme. please refer to xemics application note an8000.03 for more hints on how to use the xe88lc05 dacs. 15.1 signal dac 15.1.1 application the dac signal block described in this document converts a digital signal into an analog output signal (voltage out- put or 4-20ma loop). 15.1.2 typical external components external components are needed for the filtering of the generic dac output. these external components depend on the characteristics the customer wants to obtain. some application examples are shown in the application note an8000.03. 15.1.3 block diagram figure 15.1 shows the general block diagram of the peripheral. it consists of a control block that manages all com- munication with the cpu, sets the configuration of the peripheral and implements the different test modes. the dac converts the digital data in a pwm output signal. a completely independent amplifier is added. this allows the user to build a low impedance voltage output after the (external, probably passive) filter. it also allows to build a 4-20ma loop. (see amplifier section below for examples) figure 15.1: general block diagram 15 analog outputs xx-xe88lc01/03/05, data book page 110 20001101 preliminary in f ormation 15.1.4 the generic dac the generic dac block consists of two major parts: the noise shaper (sigma-delta modulator) and the pwm modu- lator as shown in figure 15.2. the dac word width at the input is 16 bit. if the word is narrower, 0's have to be added after the lsb to fill the 16 bits. to maintain maximum flexibility, the order of the noise shaper and the resolution of the pwm modulation are programmable by writing the codes code_lmax and ns_order to the configuration register. the possible noise shaper order is 0, 1 or 2. with noise shaper order 0, the generic dac is a conventional pwm dac which resolution can be set between 4 and 11 bits. higher resolutions are reached with higher orders of the noise shaper. the role of the sigma-delta modulator is to vary the code sent to the pwm modulator, so that its mean value is ex- actly equal to the code set in the dac input. regular way of using the dac is to set code_lmax for 4 bits (000) and ns_order to 2 (10). dacs and filter settings are explained in application note an8000.03 xe88lc05 dacs usage. 15.1.5 the amplifier the amplifier can be used in several configurations. therefore, it is not connected internally. note: 1. for the minimal resistive load and the maximal capacitive load note: 2. the amplifier common mode is vss in the 4-20ma loop (figure 6). note: 3. at dc note: 4. at dc. only a low rejection ratio is needed since the dac output refers directly to the power supplies. note: 6. short circuit protection at ~5ma. note: 7. gbw when the maximal load is cl0 and with the bit bw=0 note: 8. gbw when the maximal load is cl1 and with the bit bw=1 note: 9. in both cases bw=0 and bw=1 for the maximal capacitive load and the minimal resistive load. sym description min typ max unit comments gain gain at dc 80 db 1 gbw0 gain bandwidth product 25 khz 7 cl0 capacitive load 5 nf 7 gbw1 gain bandwidth product 125 khz 8 cl1 capacitive load 200 pf 8 fm phase margin 55 9 rl resistive load 5 kohm 6 sr slew rate 10 kv/s 10 cmr common mode input range vss-0.2 vdd-1.2 v 2 or output range vss+0.2 vdd-0.2 v voff offset 5 mv cmrr common mode rejection 60 db 3 noise integrated input noise 100 uvrms psrr power supply rejection ratio 20 db 4 ibias quiescent bias current 200 500 ua ioff off current 1 ua table 15.1: dac signal amplifier performances figure 15.2: the dac signal structure xx-xe88lc01/03/05, data book 15 analog outputs 20001101 page 111 preliminary information note: 10. for maximal load cl0, bw=0 and maximal resistive load rl 15.1.6 signal dac registers the cpu communicates with the peripheral through registers. two registers are needed for the data input, two are needed for the set-up of the peripheral. the registers are defined in table 15.2. the data in the set-up registers code for the noise shaper order (ns_order), the resolution of the pwm pulse modulation (code_lmax), the peripheral sta- tus (enable), clock input frequency (fin), if the pwm pulse is active low or high (inv) and the amplifier bandwidth. the input data will have to be resynchronized with respect to the peripheral clock. in order to guarantee the synchro- nization of the msb and lsb part of the input data, a validity flag is reset when the cpu is writing in the lsb register and set again when the cpu is writing to the msb register. the contents of the registers is not copied to the dac while the validity flag is reset. this means that the cpu always has to write the lsb register before writing the msb register. the different set-up words (set-up register definition in table 15.2) are coded as indicated in the tables below. register name address (hex) comments regdasinlsb h0068 input code (lsb) regdasinmsb h0069 input code (msb) regdascfg0 h006a dac settings regdascfg1 h006b table 15.2: signal dac registers bit name reset rw description 7-6 nsorder 0 resetsystem r w modulator order 5-3 codeimax 0 resetsystem r w pwm resolution 2-1 enable 0 resetsystem r w dac and buffer enable 0 fin 0 resetsystem r w input frequency selection table 15.3: regdascfg0 bit name reset rw description 7-2 reserved 0 resetsystem r w 1 bw 0 resetsystem r w output bandwidth selection 0 inv 0 resetsystem r w output polarity selection table 15.4: regdascfg1 ns_order(1:0) noise shaping order 00 0 (pwm operation) 01 1 1x 2 table 15.5: noise shaping setting code_lmax m (pwm resolution in bits) 000 4 001 5 010 6 011 7 100 8 101 9 110 10 111 11 table 15.6: pwm setting enable(1:0) peripheral status 00 dac: switched off; amplifier switched off table 15.7: dac status 15 analog outputs xx-xe88lc01/03/05, data book page 112 20001101 preliminary in f ormation the fin bit allows the choice between two clock inputs that can be connected in two different places of the prescaler of the xe8000. the control logic has to guarantee correct switching from one to the other. finally, the inv bit indicates if the pwm output pulse is active low or active high. this allows the use of the output amplifier in an inverting or not inverting configuration. 01 dac: normal operation; amplifier: switched off 10 dac: switched off; amplifier: normal operation 11 normal operation fin used clock input 0 rc clock 1 rc clock div 2 table 15.8: clock setting inv pwm pulse 0 active high 1 active low table 15.9: pwm polarity enable(1:0) peripheral status table 15.7: dac status xx-xe88lc01/03/05, data book 15 analog outputs 20001101 page 113 preliminary information 15.2 bias dac 15.2.1 application the bias dac block converts a digital signal into an analog output signal in dc. it can be used to bias resistive sen- sors. in some cases it could also be used to do a rough offset calibration of a resistive bridge. 15.2.2 typical external components no other external devices are needed in case of voltage controlled bridge bias. an additional resistor is needed for current controlled bridge bias. 15.2.3 block diagram figure 15.3 shows the general block diagram of the peripheral. it consists of a control block that manages all com- munication with the cpu, sets the configuration of the peripheral and implements the different test modes. the dac converts the digital data in an analog output signal. an amplifier is added in order to be able to deliver large currents. 15.2.4 the dac the dac convertor is a resistive divider connected between pads dab_r_m and dab_r_p. note: 1) time to reach the final value within 5%. note: 2) in most cases dab_r_m will be connected to vss and dab_r_p to vdd. 15.2.5 the amplifier the amplifier can be used in several configurations as for biasing a bridge in voltage or current. application exam- ples are given in application note an8000.03. sym description min typ max unit comments wda number of input bits 8 bits tstep step response 100 ms 1 range dac output range dab_r_m dab_r_p 2 table 15.10: dac performances sym description min typ max unit comments gain gain at dc 60 db 1 gbw gain bandwidth product 100 hz 1 table 15.11: amplifier performances figure 15.3: general block diagram of the bias dac 15 analog outputs xx-xe88lc01/03/05, data book page 114 20001101 preliminary in f ormation note: 1) for all possible combinations of resistive load and capacitive load. note: 2) at dc. note: 3) for voltage controlled bias control. for current controlled operation the voltage drop on the pmos output transistor has to be less than 200mv at maximum current. note: 4) special analog output pads without series resistor will be needed in order to get the specification. care has to be taken with the layout so that esd and latchup specifications can be met. note: 5) short circuit protection at ~80ma. note: 6) this amplifier must be loaded for correct operation. ibias is without load current. 15.2.6 bias dac registers fm phase margin 60 1 rl resistive load 300 100000 ohm 5,6 cl capacitive load 1 nf cmr common mode input range vss vdd v or output range vss+0.2 vdd-0.2 v 3,4 outp vr outp pin voltage range vss+2.3 vdd v voff offset 10 mv noise integrated input noise 100 uvrms isourc max source current 10 ma 5 psrr power supply rejection ratio 40 db 2 ibias quiescent bias current 2 5 ua 6 ioff off current 1 ua register name address (hex) comments regdab1in h006c input code regdab1cfg h006d dac settings table 15.12: bias dac registers enable(1:0) peripheral status 00 dac disabled, amplifier disabled 01 dac: normal operation; amplifier: switched off 10 dac: switched off; amplifier: normal operation 11 dac: enabled; amplifier: enabled table 15.13: regdab1cfg sym description min typ max unit comments table 15.11: amplifier performances xx-xe88lc01/03/05, data book 16 pin-out, package and electrical specifications 20001101 page 115 preliminary information 16 pin-out, package and electrical specifications all chips of the xe8000 family are available either as bare die or packaged. 16.1 xe88lc01 pin-out pin description position in tqfp44 function name second function name t y pe 1 pa(5) input input of port a 2 pa(6) input input of port a 3 pa(7) input input of port a 4 pc(0) input/output input-output of port c 5 pc(1) input/output input-output of port c 6 pc(2) input/output input-output of port c 7 pc(3) input/output input-output of port c 8 pc(4) input/output input-output of port c 9 pc(5) input/output input-output of port c 10 pc(6) input/output input-output of port c 11 pc(7) input/output input-output of port c 12 pb(0) testout input/output/analo g input-output-analo g of port b/ data output for test and mtp pro g ramin g / pwm output 13 pb(1) input/output/analo g input-output-analo g of port b/ pwm output 14 pb(2) input/output/analo g input-output-analo g of port b 15 pb(3) sou input/output/analo g input-output-analo g of port b, output pin of usrt 16 pb(4) scl input/output/analo g input-output-analo g of port b/ clock pin of usrt 17 pb(5) sin input/output/analo g input-output-analo g of port b/ data input or input-output pin of usrt 18 pb(6) tx input/output/analo g input-output-analo g of port b/ emission pin of uart 19 pb(7) rx input/output/analo g input-output-analo g of port b/ reception pin of uart 20 vpp/test vhi g h special test mode/hi g h volta g e for mtp pro g ramin g 21 ac_r(3) analo g hi g hest potential node for 2nd reference of adc 22 ac_r(2) analo g lowest potential node for 2nd reference of adc 23 ac_a(7) analo g adc input node pin-out of the xx-xe88lc01 in tqfp44 pinout of the xe88lc01 in tqfp44 packa g e 1 2 3 4 5 6 7 8 10 12 14 16 18 20 22 24 26 28 30 xemics xe88lc01mi n9k1444 9920 device t yp e p roduction p acka g in g date lot identification 42 32 34 36 38 40 25 27 29 31 9 16 pin-out, package and electrical specifications xx-xe88lc01/03/05, data book page 116 20001101 preliminary in f ormation 24 ac_a(6) analo g adc input node 25 ac_a(5) analo g adc input node 26 ac_a(4) analo g adc input node 27 ac_a(3) analo g adc input node 28 ac_a(2) analo g adc input node 29 ac_a(1) analo g adc input node 30 ac_a(0) analo g adc input node 31 ac_r(1) analo g hi g hest potential node for 1st reference of adc 32 ac_r(0) analo g lowest potential node for 1st reference of adc 33 vss power ne g ative power supply, connected to substrate 34 vbat power positive power supply 35 vreg analo g re g ulated supply 36 reset input reset pin (active hi g h) 37 vmult analo g pad for optional volta g e multiplier capacitor 38 oscin ck_cr analo g /input connection to xtal/ coolrisc clock for test and mtp pro g ramin g 39 oscout ptck analo g /input connection to xtal/ peripheral clock for test and mtp pro g ramin g 40 pa(0) testin input input of port a/ data input for test and mtp pro g ramin g / counter a input 41 pa(1) testck input input of port a/ data clock for test and mtp pro g ramin g / counter b input 42 pa(2) input input of port a/ counter c input/ counter capture input 43 pa(3) input input of port a/ counter d input/ counter capture input 44 pa(4) input input of port a pin description position in tqfp44 function name second function name t y pe pin-out of the xx-xe88lc01 in tqfp44 xx-xe88lc01/03/05, data book 16 pin-out, package and electrical specifications 20001101 page 117 preliminary information 16.2 xe88lc03 pin-out pin description position in so28 position in tqfp32 function name second function name t y pe 1 13 vbat power positive power supply 214vre g analo g re g ulated supply 3 15 test/vhi g hvhi g h special test mode/hi g h volta g e for mtp pro g ramin g 4 16 oscout ptck analo g /input connection to xtal/ peripheral clock for test and mtp pro g ramin g 5 17 oscin ck_cr analo g /input connection to xtal/ coolrisc clock for test and mtp pro g ramin g 6 18 vss power ne g ative power supply, connected to substrate 7 19 pa(0) testin input input of port a/ data input for test and mtp pro g ramin g / counter a input 8 20 pa(1) testck input input of port a/ data clock for test and mtp pro g ramin g / counter b input 9 21 pa(2) input input of port a/ counter c input/ counter capture input 10 22 pa(3) input input of port a/ counter d input/ counter capture input 11 23 pa(4) input input of port a 12 24 pa(5) input input of port a 13 25 pa(6) input input of port a 14 26 pa(7) input input of port a 15 27 pc(0) input/output input-output of port c 16 28 pc(1) input/output input-output of port c 17 29 pc(2) input/output input-output of port c 18 30 pc(3) input/output input-output of port c 31 pc(4) input/output input-output of port c 32 pc(5) input/output input-output of port c 1 pc(6) input/output input-output of port c 2 pc(7) input/output input-output of port c 19 3 pb(0) testout input/output/analo g input-output-analo g of port b/ data output for test and mtp pro g ramin g / pwm output 20 4 pb(1) input/output/analo g input-output-analo g of port b/ pwm output 21 5 pb(2) input/output/analo g input-output-analo g of port b 22 6 pb(3) sou input/output/analo g input-output-analo g of port b, output pin of usrt 23 7 pb(4) scl input/output/analo g input-output-analo g of port b/ clock pin of usrt pin-out of the XX-XE88LC03 in so28 and tqfp32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 xemics xx88lc03xi015 9920 vbat vre g test/vhi g h oscout oscin/freqin v g nd pa [ 0 ] pa [ 1 ] pa [ 2 ] pa [ 3 ] pa [ 4 ] pa [ 5 ] pa [ 6 ] pa [ 7 ] rcres reset pb[7] pb[6] pb[5] pb[4] pb[3] pb[2] pb[1] pb[0] pc[3] pc[2] pc[1] pc[0] pinout of the XX-XE88LC03 in sop28 packa g e pinout of the XX-XE88LC03 in tqfp32 1 2 3 4 5 6 7 810 12 14 16 18 20 22 24 26 28 30 xemics xx88lc03mi n9k1444 9920 device t yp e p roduction p acka g in g date lot identification 16 pin-out, package and electrical specifications xx-xe88lc01/03/05, data book page 118 20001101 preliminary in f ormation 24 8 pb(5) sin input/output/analo g input-output-analo g of port b/ data input or input-output pin of usrt 25 9 pb(6) tx input/output/analo g input-output-analo g of port b/ emission pin of uart 26 10 pb(7) rx input/output/analo g input-output-analo g of port b/ reception pin of uart 27 11 reset input reset pin (active hi g h) 28 12 rcres analo g optional external resistor for rc oscillator pin description position in so28 position in tqfp32 function name second function name t y pe pin-out of the XX-XE88LC03 in so28 and tqfp32 xx-xe88lc01/03/05, data book 20001101 page 119 preliminary information 16.3 xe88lc05 pin-out pin description position function name second function name type 1 pa(0) testin input input of port a/ data input for test and mtp programing/ counter a input 2 pa(1) testck input input of port a/ data clock for test and mtp programing/ counter b input 3 pa(2) input input of port a/ counter c input/ counter capture input 4 pa(3) input input of port a/ counter d input/ counter capture input 5 pa(4) input input of port a 6 pa(5) input input of port a 7 pa(6) input input of port a 8 pa(7) input input of port a 9 pc(0) input/output input-output of port c 10 pc(1) input/output input-output of port c 11 pc(2) input/output input-output of port c 12 pc(3) input/output input-output of port c 13 pc(4) input/output input-output of port c 14 pc(5) input/output input-output of port c 15 pc(6) input/output input-output of port c 16 pc(7) input/output input-output of port c 17 pb(0) testout input/output/analog input-output-analog of port b/ data output for test and mtp programing/ pwm output 18 pb(1) input/output/analog input-output-analog of port b/ pwm output 19 pb(2) input/output/analog input-output-analog of port b table 16.1: pin-out of the xe88lc05 in tqfp64 pa(0) pa(1) pa(2) pa(3) pa(4) pa(5) pa(6) pa(7) pc(0) pc(1) pc(2) pc(3) pc(4) pc(5) pc(6) pc(7) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 22 24 26 28 30 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 61 59 57 55 53 51 pb(0) pb(1) pb(2) pb(3) pb(4) pb(5) pb(6) pb(7) dab_out dab_ao_p dab_ao_m dab_ai_p dab_ai_m ac_r(0) ac_r(1) ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) ac_r(2) ac_r(3) figure 16.1: pinout of the xe88lc05 in tqfp64 package rcres oscin oscout reset vmult test vreg vss_vreg vss vbat das_out das_ai_p das_ai_m das_ao dab_r_p dab_r_m xemics xe88lc05x028 xx-xe88lc01/03/05, data book page 120 20001101 preliminary in f ormation 20 pb(3) sou input/output/analog input-output-analog of port b, output pin of usrt 21 pb(4) scl input/output/analog input-output-analog of port b/ clock pin of usrt 22 pb(5) sin input/output/analog input-output-analog of port b/ data input or input-output pin of usrt 23 pb(6) tx input/output/analog input-output-analog of port b/ emission pin of uart 24 pb(7) rx input/output/analog input-output-analog of port b/ reception pin of uart 25 dab_r_p analog positive reference of bias dac 26 dab_r_m analog negative reference of bias dac 27 dab_out analog output of bias dac 28 dab_ao_p analog highest potential output of bias dac buffer 29 dab_ao_m analog lowest potential output of bias dac buffer 30 dab_ai_p analog positive input of bias dac buffer 31 dab_ai_m analog negative input of bias dac buffer 32 not connected spare pin to be connected to negative power supply 33 test/vhigh vhigh special test mode/high voltage for mtp programing 34 not connected spare pin to be connected to negative power supply 35 ac_r(3) analog highest potential node for 2nd reference of adc 36 ac_r(2) analog lowest potential node for 2nd reference of adc 37 ac_a(7) analog adc input node 38 ac_a(6) analog adc input node 39 ac_a(5) analog adc input node 40 ac_a(4) analog adc input node 41 ac_a(3) analog adc input node 42 ac_a(2) analog adc input node 43 ac_a(1) analog adc input node 44 ac_a(0) analog adc input node 45 ac_r(1) analog highest potential node for 1st reference of adc 46 ac_r(0) analog lowest potential node for 1st reference of adc 47-50 not connected spare pins to be connected to negative power supply 51 das_out analog output of signal dac 52 das_ai_p analog positive input of signal dac buffer 53 das_ai_m analog negative input of signal dac buffer 54 das_ao analog output of signal dac buffer 55 vbat/vdd power positive power supply 56 vss power negative power supply, connected to substrate 57 vss_reg power digital negative power supply, must be equal to vss 58 vreg analog regulated supply 59 not connected spare pin to be connected to negative power supply 60 vmult analog pad for optional voltage multiplier capacitor 61 reset input reset pin (active high) 62 oscout ptck analog/input connection to xtal/ peripheral clock for test and mtp programing 63 oscin ck_cr analog/input connection to xtal/ coolrisc clock for test and mtp programing 64 rcres analog optional external resistor for rc oscillator pin description position function name second function name type table 16.1: pin-out of the xe88lc05 in tqfp64 xx-xe88lc01/03/05, data book 20001101 page 121 preliminary information 16.4 electrical specifications 16.4.1 absolute maximum ratings 16.4.2 operating conditions 16.4.3 io pins operation name value maximal voltage applied between any pin (but vpp/test) and vss 5.5 v voltage applied to any pin (but vpp/test) vss - 0.3 v to vdd + 0.3 v storage temperature (no programmed) 150 c storage temperature (programmed) 85 c table 16.2: absolute maximum ratings name value voltage applied between vdd and vss (rom version, without adc or dac) 1.2 - 5.5 v voltage applied between vdd and vss (mtp version, or rom version with adc or dac) 2.4 - 5.5 v operating temperature (rom) -40 - 125c operating temperature (mtp) -40 - 85 c table 16.3: operating conditions sym description condition min typ max unit comments port a: low threshold limit vbat = 1.2 v v port a: high threshold limit v output drop when sinking 1 ma 0.4 v output drop when sourcing 1 ma 0.4 v port a: low threshold limit vbat = 2.4 v 1v port a: high threshold limit 1.5 v output drop when sinking 1 ma v output drop when sinking 8 ma 0.4 v output drop when sourcing 1 ma v output drop when sourcing 8 ma 0.4 v port a: low threshold limit vbat = 5.0 v 2v port a: high threshold limit 3 v output drop when sinking 1 ma v output drop when sinking 8 ma 0.4 v output drop when sourcing 1 ma v output drop when sourcing 8 ma 0.4 v pull-up, pull-down resistor 50 150 kohm table 16.4: io pins performances xx-xe88lc01/03/05, data book page 122 20001101 preliminary in f ormation xx-xe88lc01/03/05, data book 17 index 20001101 page 123 preliminar y information 17 index numerics 16 bit counters 88 a absolute 121 absolute maximum ratings 121 active mode 45 adc 101 analog to digital converter 101 c capture functions 90 conventions 15 coolrisc 816 architecture 26 816 core 23 instruction set 26 counters 85 current requirement 22 h harvard 41 i input reference multiplexing 102 input signal multiplexing 101 instruction set 26 l low power 19, 22 m mode active 45 sleep 45 standby 45 mtp 17, 41 multiple time programmable flash memory 41 o operating conditions 121 operation mode 19 p pins operation 121 pipeline 23 power supply range 19 prescaler 63 pwm 92, 93 r resets 47 s sleep mode 45 standby mode 45 t timers 85 v voltage multiplier 21 voltage regulator 20 vss 15 w watchdog 85 x xe8000 17 xe88lc01 17 xe88lc02 17 xe88lc03 17 xe88lc04 18 xe88lc05 18 z zooming adc 101 17 index xx-xe88lc01/03/05, data book page 124 20001101 p re li m i nary i n f orma ti on xx-xe88lc01/03/05, data book 18 contact 20001101 page 125 preliminary information 18 contact one can contact xemics at info@xemics.com or on our web site at http://www.xemics.com. list of contacts, representatives and distributors can be found on the web at http://www.xemics.com/contact.html. application notes can be found on the web at http://www.xemics.com/downldata.html. xemics headquarters is xemics sa maladire 71 2007 neuchatel switzerland 12620001101 ? xemics 2000 a ll rights reserved. reproduction in whole or in part is pr ohibited without the prior wri tten consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not conv ey nor imply any license under patent or other industrial or intellectual property rights. xemics products are not designed, intended, authorized or warranted to be suitable for use in life-support applicat ions, devices or systems or other critical applications. inclusion of xemics products in such applications is understood to be undertaken solely at the customer?s own risk. should a customer purchase or use xemics products for any such unauthorized applic ation, the customer shall indemnify and hold xemics and its officers, employees, s ubsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. |
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